XC4013E-3PQ160I Datasheet, PDF (46/68 Pages) Xilinx, Inc – XC4000E and XC4000X Series Field Programmable Gate Arrays

Product Obsolete or Under Obsolescence
R
XC4000E and XC4000X Series Field Programmable Gate Arrays
used), and if RAM is present, the RAM content must be
unchanged.
Statistically, one error out of 2048 might go undetected.
Configuration Sequence
There are four major steps in the XC4000 Series power-up
configuration sequence.
• Configuration Memory Clear
• Initialization
• Configuration
• Start-Up
The full process is illustrated in Figure 46.
Configuration Memory Clear
When power is first applied or is reapplied to an FPGA, an
internal circuit forces initialization of the configuration logic.
When Vcc reaches an operational level, and the circuit
passes the write and read test of a sample pair of configu-
ration bits, a time delay is started. This time delay is nomi-
nally 16 ms, and up to 10% longer in the low-voltage
devices. The delay is four times as long when in Master
Modes (M0 Low), to allow ample time for all slaves to reach
a stable Vcc. When all INIT pins are tied together, as rec-
ommended, the longest delay takes precedence. There-
fore, devices with different time delays can easily be mixed
and matched in a daisy chain.
This delay is applied only on power-up. It is not applied
when re-configuring an FPGA by pulsing the PROGRAM
pin
X2
X15
X16
01
2 3 4 5 6 7 8 9 10 11 12 13 14
15
SERIAL DATA IN
Polynomial: X16 + X15 + X2 + 1
1 1 1 1 1 0 15 14 13 12 11 10 9 8 7 6 5
LAST DATA FRAME
CRC – CHECKSUM
Readback Data Stream
X1789
Figure 45: Circuit for Generating CRC-16
Boundary Scan
Instructions
Available:
V_CC
No
>3.5 V
Yes
Test M0 Generate
One Time-Out Pulse
of 16 or 64 ms
Keep Clearing
Configuration Memory
PROGRAM
= Low
Yes
EXTEST*
SAMPLE/PRELOAD _{Completely Clear}
BYPASS
Configuration Memory
CONFIGURE*
Once More
(* if PROGRAM = High)
~1.3 µs per Frame
INIT
High? if
Master
Yes
No
Master Waits 50 to 250 µs
Before Sampling Mode Lines
Sample
Mode Lines
Master CCLK
Goes Active
Load One
Configuration
Data Frame
SAMPLE/PRELOAD
BYPASS
Frame
Yes
Error
No
Config-
uration
No
memory
Full
Yes
Pass
Configuration
Data to DOUT
Pull INIT Low
and Stop
CCLK
Count Equals ^No
Length
Count
Yes
Start-Up
Sequence
F
EXTEST
SAMPLE PRELOAD
BYPASS
USER 1
USER 2
CONFIGURE
READBACK
Operational
If Boundary Scan
is Selected
X6076
Figure 46: Power-up Configuration Sequence
6-50
May 14, 1999 (Version 1.6)