XC4013E-3PQ160I Datasheet, PDF (35/68 Pages) Xilinx, Inc – XC4000E and XC4000X Series Field Programmable Gate Arrays

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XC4000E and XC4000X Series Field Programmable Gate Arrays
The top and bottom Global Early buffers are about 1 ns
slower clock to out than the left and right Global Early buff-
ers.
The Global Early buffers can be driven by either semi-ded-
icated pads or internal logic. They share pads with the Glo-
bal Low-Skew buffers, so a single net can drive both global
buffers, as described above.
GND
Ground and
Vcc Ring for
I/O Drivers
To use a Global Early buffer, place a BUFGE element in a
schematic or in HDL code. If desired, attach a LOC
attribute or property to direct placement to the designated
location. For example, attach a LOC=T attribute or property
to direct that a BUFGE be placed in one of the two Global
Early buffers on the top edge of the device, or a LOC=TR to
indicate the Global Early buffer on the top edge of the
device, on the right.
Power Distribution
Vcc
Vcc
Logic
Power Grid
GND
X5422
Figure 39: XC4000 Series Power Distribution
Power for the FPGA is distributed through a grid to achieve _{Pin Descriptions}
high noise immunity and isolation between logic and I/O.
Inside the FPGA, a dedicated Vcc and Ground ring sur-
rounding the logic array provides power to the I/O drivers,
There are three types of pins in the XC4000 Series
devices:
as shown in Figure 39. An independent matrix of Vcc and • Permanently dedicated pins
Ground lines supplies the interior logic of the device.
• User I/O pins that can have special functions
6
This power distribution grid provides a stable supply and ^{• Unrestricted user-programmable I/O pins.}
ground for all internal logic, providing the external package Before and during configuration, all outputs not used for the
power pins are all connected and appropriately de-coupled. configuration process are 3-stated with a 50 kΩ - 100 kΩ
Typically, a 0.1 µF capacitor connected between each Vcc pull-up resistor.
pin and the board’s Ground plane will provide adequate
de-coupling.
After configuration, if an IOB is unused it is configured as
an input with a 50 kΩ - 100 kΩ pull-up resistor.
Output buffers capable of driving/sinking the specified 12
mA loads under specified worst-case conditions may be
capable of driving/sinking up to 10 times as much current
under best case conditions.
XC4000 Series devices have no dedicated Reset input.
Any user I/O can be configured to drive the Global
Set/Reset net, GSR. See “Global Set/Reset” on page 11
for more information on GSR.
Noise can be reduced by minimizing external load capaci-
tance and reducing simultaneous output transitions in the
same direction. It may also be beneficial to locate heavily
loaded output buffers near the Ground pads. The I/O Block
output buffers have a slew-rate limited mode (default) which
should be used where output rise and fall times are not
speed-critical.
XC4000 Series devices have no Powerdown control input,
as the XC3000 and XC2000 families do. The
XC3000/XC2000 Powerdown control also 3-stated all of the
device
I/O pins. For XC4000 Series devices, use the global 3-state
net, GTS, instead. This net 3-states all outputs, but does
not place the device in low-power mode. See “IOB Output
Signals” on page 23 for more information on GTS.
Device pins for XC4000 Series devices are described in
Table 16. Pin functions during configuration for each of the
seven configuration modes are summarized in Table 22 on
page 58, in the “Configuration Timing” section.
May 14, 1999 (Version 1.6)
6-39