XC4013E-3PQ160I Datasheet, PDF (36/68 Pages) Xilinx, Inc – XC4000E and XC4000X Series Field Programmable Gate Arrays

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XC4000E and XC4000X Series Field Programmable Gate Arrays
Table 16: Pin Descriptions
I/O
I/O
During After
Pin Name Config. Config.
Pin Description
Permanently Dedicated Pins
Eight or more (depending on package) connections to the nominal +5 V supply voltage
VCC
I
I (+3.3 V for low-voltage devices). All must be connected, and each must be decoupled
with a 0.01 - 0.1 µF capacitor to Ground.
GND
I
I
Eight or more (depending on package type) connections to Ground. All must be con-
nected.
During configuration, Configuration Clock (CCLK) is an output in Master modes or Asyn-
chronous Peripheral mode, but is an input in Slave mode and Synchronous Peripheral
CCLK
I or O
I
mode. After configuration, CCLK has a weak pull-up resistor and can be selected as the
Readback Clock. There is no CCLK High or Low time restriction on XC4000 Series de-
vices, except during Readback. See “Violating the Maximum High and Low Time Spec-
ification for the Readback Clock” on page 56 for an explanation of this exception.
DONE is a bidirectional signal with an optional internal pull-up resistor. As an output, it
indicates the completion of the configuration process. As an input, a Low level on DONE
DONE
I/O
O can be configured to delay the global logic initialization and the enabling of outputs.
The optional pull-up resistor is selected as an option in the XACTstep program that cre-
ates the configuration bitstream. The resistor is included by default.
PROGRAM is an active Low input that forces the FPGA to clear its configuration mem-
ory. It is used to initiate a configuration cycle. When PROGRAM goes High, the FPGA
PROGRAM
I
I
finishes the current clear cycle and executes another complete clear cycle, before it
goes into a WAIT state and releases INIT.
The PROGRAM pin has a permanent weak pull-up, so it need not be externally pulled
up to Vcc.
User I/O Pins That Can Have Special Functions
During Peripheral mode configuration, this pin indicates when it is appropriate to write
another byte of data into the FPGA. The same status is also available on D7 in Asyn-
RDY/BUSY
O
I/O chronous Peripheral mode, if a read operation is performed when the device is selected.
After configuration, RDY/BUSY is a user-programmable I/O pin.
RDY/BUSY is pulled High with a high-impedance pull-up prior to INIT going High.
During Master Parallel configuration, each change on the A0-A17 outputs (A0 - A21 for
RCLK
O
I/O
XC4000X) is preceded by a rising edge on RCLK, a redundant output signal. RCLK is
useful for clocked PROMs. It is rarely used during configuration. After configuration,
RCLK is a user-programmable I/O pin.
As Mode inputs, these pins are sampled after INIT goes High to determine the configu-
ration mode to be used. After configuration, M0 and M2 can be used as inputs, and M1
can be used as a 3-state output. These three pins have no associated input or output
registers.
I (M0), During configuration, these pins have weak pull-up resistors. For the most popular con-
M0, M1, M2
I O (M1), figuration mode, Slave Serial, the mode pins can thus be left unconnected. The three
I (M2) mode inputs can be individually configured with or without weak pull-up or pull-down re-
sistors. A pull-down resistor value of 4.7 kΩ is recommended.
These pins can only be used as inputs or outputs when called out by special schematic
definitions. To use these pins, place the library components MD0, MD1, and MD2 in-
stead of the usual pad symbols. Input or output buffers must still be used.
If boundary scan is used, this pin is the Test Data Output. If boundary scan is not used,
this pin is a 3-state output without a register, after configuration is completed.
TDO
O
O This pin can be user output only when called out by special schematic definitions. To
use this pin, place the library component TDO instead of the usual pad symbol. An out-
put buffer must still be used.
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May 14, 1999 (Version 1.6)