DS669 Datasheet, PDF (9/28 Pages) Xilinx, Inc – AXI Interface Based

AXI Interface Based KC705 Embedded Kit MicroBlaze Processor Subsystem Data Sheet
The axi4lite_0 interconnect is for masters and slaves that are geared for the AXI4-Lite™ protocol (32-bit interface, supports
only single transactions). This includes masters like the MicroBlaze processor instruction port and data port. In this design,
the MicroBlaze processor instruction port is not connected. Slaves connected to this interconnect have register maps or user
logic that does not contain high-speed logic like bursting. The axi_gpio and axi_timer IP cores are examples of slaves
connected to the axi4lite_0 interconnect.
Interrupt Controller Configuration
The axi_intc contains one AXI4-Lite interface slave connection. The master connected to the axi_intc on the axi4lite_0
interconnect is the MicroBlaze processor DP. The MicroBlaze processor subsystem shows the internal interrupts generated
in the embedded system and the priority ordering of the interrupts (Table 4).
Table 4: MicroBlaze Processor Subsystem Interrupt Priorities
Signal
AXI_DMA_Ethernet_mm2s_introut⁽¹⁾
Source
axi_dma
Description
Transmit complete interrupt from the DMA.
AXI_DMA_Ethernet_s2mm_introut
axi_dma
Receive complete interrupt from the DMA.
Soft_Ethernet_MAC_INTERRUPT
axi_ethernet
Interrupt condition in the Ethernet has occurred, as indicated in the
TEMAC Interrupt Status register.
Dual_Timer_Counter_Interrupt
axi_timer
In Generate Mode, indicates that the counter rolled over. In Capture
Mode, the interrupt event is the capture event.
IIC_EEPROM_Intr
axi_iic
Interrupt condition in the IIC controller has occurred, as indicated in
the IIC Interrupt Status register.
RS232_Uart_1_Intr
axi_uart16550
Interrupt condition in the UART 16550 has occurred, as indicated in
the UART Interrupt Identification register.
logisdhc_0_interrupt
xadc_Irpt⁽²⁾
logisdhc
axi_xadc
Interrupt from SDHC Controller.
Interrupt condition in the XADC has occurred, as indicated in the
XADC Interrupt Status register.
Notes:
1. This signal has highest priority.
2. This signal has lowest priority.
3. The IP core data sheets are easily accessed within XPS by right-clicking on the IP core of interest and selecting View PDF Data Sheet.
4. For more information about the interrupt controller, see the axi_intc data sheet.
5. For specific information about the interrupt outputs generated by the peripherals in the system, see the corresponding IP core's data sheet.
Dual Timer/Counter
The axi_timer contains one AXI4-Lite interface slave connection. The master connected to the axi_timer through the shared
mode on the axi4lite_0 interconnect is the MicroBlaze processor DP. The axi_timer core is configured to provide two 32-bit
timers.
debug_module
This instance includes a UART with a configurable slave bus interface that is configured for the AXI4-Lite interface. The
MicroBlaze processor DP port is the master connected to the debug_module slave connections through the shared mode on
the axi4lite_0 interconnect. The UART TX and RX signals are transmitted over the FPGA JTAG port to and from the Xilinx
Microprocessor Debug (XMD) tool.
axi_bram_ctrl Configuration
The axi_bram_ctrl contains one AXI4 interface slave connection. The slave’s data width is configured for 32 bits using the
AXI4 interface. Masters connected to the axi_bram_ctrl are the MicroBlaze processor I-cache and D-cache through the
AXI_4_0 interconnect, by means of the shared mode.
The C_S_AXI_SUPPORTS_NARROW_BURST is set to zero because all masters inside the system are 32 bits. This
parameter should be set to one when connecting to masters bigger than 32 bits inside the design. Setting the parameter to
zero allows for resource savings.
DS669 (v2.0) April 23, 2013
www.xilinx.com
Product Specification
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