DS669 Datasheet, PDF (8/28 Pages) Xilinx, Inc – AXI Interface Based

AXI Interface Based KC705 Embedded Kit MicroBlaze Processor Subsystem Data Sheet
Table 3: Clock Generator Configuration Settings (Cont’d)
Component
Frequency
(MHz)
Phase
logisdhc_0
• sd_base_clk
100.000000
0
• S_AXI_ACLK
100.000000
0
Top-Level Output Clock Ports
• ddr_ck
800.000000
0
• sd_clk
12.500000
0
Buffered
TRUE
TRUE
FALSE
FALSE
Reset
Resets for the MicroBlaze processor subsystem are generated from the active-High reset input from the board. The external
board reset is filtered and synchronized to the system clock. The AXI interconnect reset signals are active-Low and are
sequenced coming out of reset in this order:
1. Bus structures come out of reset.
2. Peripheral(s) come out of reset 16 clocks later.
3. The CPU comes out of reset 16 clocks after the peripherals
Resets to the MicroBlaze processor subsystem are generated by the Proc Sys Reset IP core.
MicroBlaze Processor Configuration
The MicroBlaze processor is configured for performance optimization with a hardware barrel shifter and an MMU, and is
optimized for speed.
The hardware barrel shifter can shift or rotate a data word by any number of bits in a single clock cycle. Data shifting is a
required element of many key operations such as address generation and arithmetic functions. The action of a barrel shifter
can be emulated in software, but this takes valuable time which is not available in real-time applications.
In the processor subsystem, full MMU functionality is enabled, including virtual memory address translation. In virtual mode,
the MMU translates effective addresses into physical addresses. The MMU also supports memory protection, which allows
small blocks of memory to be individually protected from unauthorized access.
The I-cache master and D-cache master are both enabled, each with a cache size of 8 KB. In addition, the I-cache and
D-cache execute burst transactions up to eight data beats (8 x 32-bits). The cacheable block of the system is accessed
through the axi4_0 interconnect where the Kintex-7 FPGA AXI DDRX memory controller and other high-speed slave
peripherals are connected. The data port (DP) master of the MicroBlaze processor is enabled and connected to the
axi4lite_0 interconnect where the low-speed slaves (like the axi_gpio and axi_timer) are connected (slaves that have register
functionality or slaves that don’t generate burst transactions).
Exceptions are generated for all illegal op codes, unaligned data accesses, and bus errors. More information about the
MMU, exceptions, I-cache, D-cache, and performance optimization can be found in the MicroBlaze Processor Reference
Guide Embedded Development Kit [Ref 2].
AXI Interconnect Configuration
There are three AXI interconnects inside the KC705 MicroBlaze processor subsystem: axi4_0, axi_mm_mb, and axi4lite_0.
The axi4_0 and axi_mm_mb interconnects are for masters and slaves that fully utilize the AMBA® AXI4™ protocol. This
includes masters like the MicroBlaze processor I-cache and D-cache, and axi_dma masters. The axi_7series_ddrx is
connected as a slave to this interconnect. This system is a subset of the video demonstration system which has four AXI
interconnects connected in hierarchical fashion. The hierarchical connection allows better timing closure and expansion of
current hardware to support more AXI masters. It also helps in better floorplanning of the design. In this system also, the two
interconnects (axi4_0 and axi_4_0_mb) are connected in hierarchical fashion, which allows design symmetry with the video
demonstration design where multiple masters and slaves are connected through multiple interconnects to share the load.
DS669 (v2.0) April 23, 2013
www.xilinx.com
Product Specification
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