DS669 Datasheet, PDF (10/28 Pages) Xilinx, Inc – AXI Interface Based

AXI Interface Based KC705 Embedded Kit MicroBlaze Processor Subsystem Data Sheet
axi_7series_ddrx Configuration
The axi_7series_ddrx allows the user to use the Memory Interface Generator (MIG) to configure the memory controller. The
axi_7series_ddrx contains one AXI4 interface slave connection. The slave’s data width is configured for 512 bits. The DDRX
controller is configured to support data throughput up to 100 Gb/s (512 bits x 200 MHz) whereas a 64-bit DDR memory can
also support up to 100 Gb/s with an operating frequency of 800 MHz (64 bits x 1.6 Gb/s).
Masters connected to the axi_7series_ddrx through the AXI MM interconnects are I-cache and D-cache ports of the
MicroBlaze processor, scatter-gather (SG), memory-map-to-stream (MM2S), and stream-to-memory-map (S2MM) ports of
the DMA Ethernet controller. Masters have the ability of issuing one or more transactions to the interconnect. The read
acceptance and write acceptance limit of the axi_7series_ddrx controller are both set to 32.
IIC Controller Configuration
The axi_iic contains one AXI4-Lite interface slave connection. The master connected to the axi_iic through the shared mode
on the axi4lite_0 interconnect is the MicroBlaze processor DP.
The IIC controller supports 7-bit or 10-bit addressing and contains 16-byte transmit and receive FIFOs. It can be configured
for standard mode operation (100 KHz) or fast mode operation (>100 KHz–400 KHz).
In the MicroBlaze processor subsystem, the IIC controller is used to interface to the IIC EEPROM and is configured for
standard mode operation (100 KHz) with 7-bit addressing.
Linear Flash Controller Configuration
The axi_emc contains one AXI4-Lite interface slave connection. The master connected to the axi_emc through the shared
mode on the axi4lite_0 interconnect is the MicroBlaze processor DP.
The axi_emc is used to interface with the external linear flash device (16-bit wide 128 Mb Numonyx Flash device
PC28F00AP30TF). The flash controller is configured to execute multiple memory access cycles to match memory bank x
data width to AXI data width (C_INCLUDE_DATAWIDTH_MATCHING_0 = 1).
GPIO Configuration
The axi_gpio contains one AXI4-Lite interface slave connection. The master connected to the axi_gpio instances through
the shared mode on the axi4lite_0 interconnect is the MicroBlaze processor DP.
The axi_gpio core is instantiated five times in the system to allow the embedded system to control and access the
pushbuttons (Push_Buttons_5Bits), DIP switches (DIP_Switches_4Bits), LCD interface (LCD_GPIO), rotary switch
(ROTARY_GPIO), and LEDs (LEDs_8Bits).
• The Push_Buttons_5Bits instance is an input-only GPIO with a width of 5 bits.
• The DIP_Swithes_4Bits instance is an input-only GPIO with a width of 4 bits.
• The LEDs_8Bits instance is an output-only GPIO with a width of 8 bits.
• The LCD_GPIO instance is an output-only GPIO with a width of 7 bits.
• The ROTARY_GPIO instance is an input-only GPIO with a width of 3 bits.
UART Configuration
The axi_uart16550 contains one AXI4-Lite interface slave connection. The master connected to the axi_uart16550 through
the shared mode on the axi4lite_0 interconnect is the MicroBlaze processor DP.
The UART core is configured to use interrupts. The baud rate, data bits, and parity settings are controlled through software.
axi_dma
The axi_dma is connected to the axi_ethernet by means of the AXI-Stream protocol. The AXI-Stream interface width is
32 bits for the axi_ethernet. The MM2S interface is equivalent to transmit (TX) and the S2MM is equivalent to receive (RX).
The MM2S, S2MM, and SG interfaces are connected to the AXI_4_0 interconnect. The axi4lite_0 connection of the core is
connected to the axi4lite_0 interconnect.
DS669 (v2.0) April 23, 2013
www.xilinx.com
Product Specification
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