DS669 Datasheet, PDF (22/28 Pages) Xilinx, Inc – AXI Interface Based

AXI Interface Based KC705 Embedded Kit MicroBlaze Processor Subsystem Data Sheet
Reset
Configuration details are the same as in the BIST system (see Reset, page 8).
MicroBlaze Processor Configuration
Configuration details are the same as in the BIST system (see MicroBlaze Processor Configuration, page 8).
Dual Timer/Counter
Configuration details are the same as in the BIST system (see Dual Timer/Counter, page 9).
debug_module
Configuration details are the same as in the BIST system (see debug_module, page 9).
axi_bram_ctrl Configuration
Configuration details are the same as in the BIST system (see axi_bram_ctrl Configuration, page 9).
axi_7series_ddrx Configuration
Configuration details are the same as in the BIST system (see axi_7series_ddrx Configuration, page 10).
IIC Controller Configuration
Configuration details are the same as in the BIST system (see IIC Controller Configuration, page 10).
Linear Flash Controller Configuration
Configuration details are the same as in the BIST system (see Linear Flash Controller Configuration, page 10).
GPIO Configuration
Configuration details are the same as in the BIST system (see GPIO Configuration, page 10).
UART Configuration
Configuration details are the same as in the BIST system (see UART Configuration, page 10).
axi_dma
Configuration details are the same as in the BIST system (see axi_dma, page 10).
Ethernet Configuration
Configuration details are the same as in the BIST system (see Ethernet Configuration, page 11).
axi_xadc Configuration
Configuration details are the same as in the BIST system (see axi_xadc Configuration, page 11).
logisdhc Configuration
Configuration details are the same as in the BIST system (see logisdhc Configuration, page 11).
AXI Interconnect Configuration
Two types of interconnects are implemented in the system. The AXI_MM type interconnect is for masters and slaves that
fully utilize the AXI4 protocol for high-throughput data exchange. The AXI_Lite type is for masters and slaves that are geared
for the AXI4-Lite protocol (32-bit interface, supports only single transactions).
Four AXI_MM interconnects (axi4_0, axi_mm_mb, axi_mm_video12, and axi_mm_video34) are connected in a hierarchical
fashion. This allows for better timing closure and expansion of current hardware to support more AXI masters. It also helps
in floorplanning of the design. The axi4_0 interconnect is configured for 512-bit width and operates at 200 MHz. A total of 12
masters are connected in the design, and the DDRX controller is the only slave connected to axi4_0 that is accessible to all
the masters.
DS669 (v2.0) April 23, 2013
www.xilinx.com
Product Specification
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