DS669 Datasheet, PDF (23/28 Pages) Xilinx, Inc – AXI Interface Based

AXI Interface Based KC705 Embedded Kit MicroBlaze Processor Subsystem Data Sheet
The design is partitioned so that the MicroBlaze processor and Ethernet DMA are connected to axi_mm_mb, the first two
video pipelines (four VDMA masters) are connected to axi_mm_video12, the last two video pipelines (four VDMA masters)
are connected to axi_mm_video34, and finally, the three interconnects are connected to the axi4_0 interconnect through the
axi2axi connector. Apart from this, the logiCVC display controller is another master on the axi4_0 interconnect. This design
can be expanded to support more video pipelines to either axi_mm_video12 or axi_mm_video34 interconnects. Each of
these two interconnects can support 12 more masters.
Two AXI_Lite interconnects (axi4lite_0 and axi4lite_1) are connected in hierarchical fashion. The MicroBlaze processor is
the master for axi4lite_0, and through the axi2axi connector, axi4lite_1 is connected as one of the slaves to axi4lite_0.
Slaves connected to this interconnect have register maps or user logic that does not contain high-speed logic like bursting.
A total of 32 slaves are connected to the MicroBlaze processor through these two interconnects. All interconnects are
configured for 32-bit widths and operate at 100 MHz. The axi_gpio and axi_timer IP cores are examples of slaves connected
to the axi4lite_0 interconnect.
Video Source Select
Video Source Select multiplexes between internally generated test patterns or external video. The output of this block is
given to the DVI2AXI block. Selection is through a GPIO register bit (position 4 of the GPIO reset register: 0x40C00000).
Two instances of this block handle multiplexing of the two external video streams.
Video Timing Controller
The v_tc is one of the AXI_Lite slaves to the MicroBlaze processor connected through the axi4lite_0 interconnect. Time base
is configured to work in generate mode by setting the parameter GENERATE_EN. It is configured to generate timing control
signals for a video resolution of 1080p. Timing control signals generated from this block are common for all the video test
patterns generated internally.
DVI2AXI
This block converts a video input consisting of parallel video data, video syncs, blanks, and data enable to an AXI4-Stream™
master bus that follows the AXI4-Stream Video protocol. This functionality is achieved using Video In to AXI4-Stream core.
This core handles the asynchronous clock boundary crossing between the video clock domain and the AXI4-Stream clock
domain. Two instances of this IP are implemented in the system to support two external video streams.
AXI_SCALAR
This block scales down the video frame by a factor of four, i.e., from a 1920 x 1080 input resolution, AXI_SCALAR generates
video with a resolution of 960 x 540. It has two streaming interfaces that are connected to the S2MM and MM2S channels
of Scalar VDMA. Two instances of this IP are connected to scale two video pipelines.
DVI_SCALAR
This block scales down the video frame by a factor of four. The functionality of DVI_SCALAR is the same as AXI_SCALAR,
provided it scales the video image dynamically before writing it into the memory. However, AXI_SCALAR reads the frame
from memory, scales it, and writes it back to the frame in a different location of the memory. The input interface of this block
is the DVI interface, and the output interface is a streaming interface towards the S2MM channel of the TPG VDMA. Two
instances of this IP are connected to two scale video pipelines.
axi_tpg
The axi_tpg contains one AXI4-Lite interface slave connection. The master connected to the axi_tpg on the axi4lite_0
interconnect is the MicroBlaze processor DP. Different video patterns can be generated inside the FPGA by configuring
pattern select registers. Four instances of the IP are implemented in the system to generate four different test patterns.
DVI_IN_0_VDMA
DVI_IN_0_VDMA has two interfaces: one is the 32-bit streaming interface towards the DVI2AXI block, and the other is a
64-bit AXI MM interface towards the axi_mm_video12 interconnect. The S2MM channel is enabled, and the
C_PRMRY_IS_ACLK_ASYNC parameter is set because the clocks connected to the VDMA are of different frequencies.
User register slices on all channels are set to 8. The S2MM line buffer is set to 4096, and the burst length is set to 256. Write
FIFO delay in the interconnect settings is enabled with a FIFO delay of 512. The AXI MM and AXI Streaming interfaces
DS669 (v2.0) April 23, 2013
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Product Specification
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