DS669 Datasheet, PDF (18/28 Pages) Xilinx, Inc – AXI Interface Based

AXI Interface Based KC705 Embedded Kit MicroBlaze Processor Subsystem Data Sheet
Table 6: KC705 MicroBlaze Processor Subsystem Address Map (Cont’d)
Instance
Peripheral
Base Address
High Address
Soft_Ethernet_MAC
axi_ethernet
0x50100000
0X5013FFFF
axi_tpg_dvi_0
axi_tpg
0x50200000
0x5020FFFF
DVI_IN_0_VDMA
axi_vdma
0x50300000
0x5030FFFF
SCALER_0_VDMA
axi_vdma
0x50400000
0x5040FFFF
timebase_0
v_tc
0x50500000
0X5050FFFF
axi_tpg_0
axi_tpg
0x50600000
0x5060FFFF
TPG_0_VDMA
axi_vdma
0x50700000
0X5070FFFF
axi_tpg_dvi_1
axi_tpg
0x50800000
0x5080FFFF
DVI_IN_1_VDMA
axi_vdma
0x50900000
0X5090FFFF
SCALER_2_VDMA
axi_vdma
0x50A00000
0X50A0FFFF
axi_tpg_2
axi_tpg
0x50B00000
0x50B0FFFF
TPG_2_VDMA
axi_vdma
0x50C00000
0X50C0FFFF
CVC_DISPLAY
logicvc
0x80000000
0x9FFFFFFF
Internal_BRAM
axi_bram_ctrl
0xC0000000
0xC000FFFF
DDR3_SDRAM
axi_7series_ddrx
0x80000000
0xBFFFFFFF
Video Demonstration System Configuration
Clocking Methodology and Considerations
This is the same as in the BIST system (see Clocking Methodology and Considerations, page 5).
Clock Generator Configuration
Clocks are generated by the clock generator. Based on the user’s clock configuration inputs, the clock generator determines
the correct configuration of the PLLs. The clock generator configuration wizard is invoked by selecting Hardware > Launch
Clock Wizard. The clock generator configuration settings are shown in Table 7.
Table 7: Clock Generator Configuration Settings
Component
Frequency
(MHz)
Phase
Input Clock
CLK
200.000000
Processor
microblaze_0
150.000000
0
Buses
axi4_0
150.000000
0
axi4lite_0
100.000000
0
Peripherals
proc_sys_reset_0
• Slowest_sync_clk
100.000000
0
Interrupt_Cntlr
• S_AXI_ACLK
100.000000
0
ilmb
• LMB_CLK
150.000000
0
Buffered
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
DS669 (v2.0) April 23, 2013
www.xilinx.com
Product Specification
18