DS669 Datasheet, PDF (25/28 Pages) Xilinx, Inc – AXI Interface Based

AXI Interface Based KC705 Embedded Kit MicroBlaze Processor Subsystem Data Sheet
are set to 8. The FIFO depth towards the interconnect is set as 512. Frame sync for each layer is controlled by the frame
sync out of the VDMAs corresponding to each video pipeline.
Interrupt Controller Configuration
The axi_intc contains one AXI4-Lite interface slave connection. The master connected to the axi_intc on the axi4lite_0
interconnect is the MicroBlaze processor DP. Table 8 shows the internal interrupts generated in the embedded system and
the priority ordering of the interrupts.
Table 8: MicroBlaze Processor Subsystem Interrupt Priorities
Signal
AXI_DMA_Ethernet_mm2s_introut⁽¹⁾
Source
axi_dma
Description
Transmit complete interrupt from the DMA.
AXI_DMA_Ethernet_s2mm_introut
axi_dma
Receive complete interrupt from the DMA.
Soft_Ethernet_MAC_INTERRUPT
axi_ethernet
Interrupt condition in the Ethernet has occurred, as indicated in the
TEMAC Interrupt Status register.
Dual_Timer_Counter_Interrupt
axi_timer
In Generate mode, indicates that the counter rolled over. In Capture
mode, the interrupt event is the capture event.
IIC_EEPROM_Intr
axi_iic
Interrupt condition in the IIC controller has occurred, as indicated in
the IIC Interrupt Status register.
RS232_Uart_1_Intr
axi_uart16550
Interrupt condition in the UART 16550 has occurred, as indicated in
the UART Interrupt Identification register.
logisdhc_0_interrupt
logisdhc
Interrupt from SDHC controller.
DVI_IN_0_VDMA_s2mm_introut
DVI_IN_0_VDMA S2MM interrupt from DVI_IN_0 VDMA.
SCALER_0_VDMA_mm2s_introut
SCALER_0_VDMA MM2S interrupt from Scaler_0 VDMA.
SCALER_0_VDMA_s2mm_introut
SCALER_0_VDMA S2MM interrupt from Scaler_0 VDMA.
timebase_0_IP2INTC_Irpt
timebase_0
Interrupt from the VTC timing control signal generator.
TPG_0_VDMA_s2mm_introut
TPG_0_VDMA
S2MM interrupt from TPG_0_VDMA.
DVI_IN_1_VDMA_s2mm_introut
DVI_IN_1_VDMA S2MM interrupt from DVI_IN_1_VDMA.
SCALER_2_VDMA_mm2s_introut
SCALER_2_VDMA MM2S interrupt from Scalre_2 VDMA.
SCALER_2_VDMA_s2mm_introut
SCALER_2_VDMA S2MM interrupt from Scalre_2 VDMA.
TPG_2_VDMA_s2mm_introut
TPG_2_VDMA
S2MM interrupt from TPG_2_VDMA.
CVC_DISPLAY_interrupt
xadc_Irpt⁽²⁾
logiCVC
axi_xadc
Interrupt from logiCVC.
Interrupt condition in the XADC has occurred, as indicated in the
XADC Interrupt Status register.
Notes:
1. This signal has highest priority.
2. This signal has lowest priority.
3. The IP core data sheets are easily accessed within XPS by right-clicking on the IP core of interest and selecting View PDF Data Sheet.
4. For more information about the interrupt controller, see the axi_intc data sheet.
5. For specific information about the interrupt outputs generated by the peripherals in the system, see the corresponding IP core data sheet.
Video Demonstration Application and Board Support Package
This section provides a description of the software application and its associated board support package that are provided
with this system (Table 9).
Table 9: KC705 MicroBlaze Processor Subsystem Software Application
Software Platform
Software Application
Xilkernel
Video_Demo
DS669 (v2.0) April 23, 2013
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Product Specification
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