DS669 Datasheet, PDF (20/28 Pages) Xilinx, Inc – AXI Interface Based

AXI Interface Based KC705 Embedded Kit MicroBlaze Processor Subsystem Data Sheet
Table 7: Clock Generator Configuration Settings (Cont’d)
Component
Frequency
(MHz)
Phase
Buffered
• AXI_STR_RXD_ACLK
150.000000
0
TRUE
• AXI_STR_RXS_ACLK
150.000000
0
TRUE
• GTX_CLK
125.000000
0
TRUE
• REF_CLK
200.000000
0
TRUE
axi_xadc_0
• S_AXI_ACLK
100.000000
0
TRUE
logisdhc_0
• sd_base_clk
100.000000
0
TRUE
• S_AXI_ACLK
100.000000
0
TRUE
axi_tpg_dvi_0
• S_AXI_ACLK
100.000000
0
TRUE
• clk
150.000000
0
TRUE
DVI_0_2_AXI_SM
• fmc_hpc_dvidp_dvii_clk 150.000000
0
TRUE
• m_axi_s2mm_aclk
150.000000
0
TRUE
DVI_IN_0_VDMA
• s_axis_s2mm_aclk
150.000000
0
TRUE
• s_axi_lite_aclk
100.000000
0
TRUE
• m_axi_s2mm_aclk
150.000000
0
TRUE
SCALER_0_VDMA
• s_axis_s2mm_aclk
150.000000
0
TRUE
• m_axis_mm2s_aclk
150.000000
0
TRUE
• m_axi_s2mm_aclk
150.000000
0
TRUE
• m_AXI_MM2S_aclk
150.000000
0
TRUE
• s_axi_lite_aclk
100.000000
0
TRUE
SCALER_0
• m_AXI_MM2S_aclk
150.000000
0
TRUE
• m_axi_s2mm_aclk
150.000000
0
TRUE
timebase_0
• video_clk_in
150.000000
0
TRUE
axi_tpg_0
• S_AXI_ACLK
100.000000
0
TRUE
• clk
150.000000
0
TRUE
TPG_0_SCALE_2_AXI_SM
• fmc_hpc_dvidp_dvii_clk 150.000000
0
TRUE
• m_axi_s2mm_aclk
150.000000
0
TRUE
TPG_0_VDMA
• s_axis_s2mm_aclk
150.000000
0
TRUE
• s_axi_lite_aclk
100.000000
0
TRUE
• m_axi_s2mm_aclk
150.000000
0
TRUE
DS669 (v2.0) April 23, 2013
www.xilinx.com
Product Specification
20