DS669 Datasheet, PDF (24/28 Pages) Xilinx, Inc – AXI Interface Based

AXI Interface Based KC705 Embedded Kit MicroBlaze Processor Subsystem Data Sheet
operate at 150 MHz, and the AXI-Lite interface operates at 100 MHz. The MicroBlaze processor acts as a master for the Lite
interface of the VDMA that is used for register configuration.
SCALER_0_VDMA
SCALER_0_VDMA has four interfaces: two are 32-bit streaming interfaces towards the AXI_SCALAR block, and the other
two are a 64-bit AXI MM interface towards the axi_mm_video12 interconnect. Both S2MM and MM2S channels are enabled,
and the C_PRMRY_IS_ACLK_ASYNC parameter is set because clocks connected to the VDMA are of different
frequencies. User register slices on all channels are set to eight. The S2MM line buffer is set to 4096, and burst length is set
to 256. The MM2S line buffer is set to 256, and the burst length is set to 256. Write FIFO delay in the interconnect settings
is enabled with a FIFO delay of 512. The AXI MM and AXI Streaming interfaces operate at 150 MHz, and the AXI-Lite
interface operates at 100 MHz. The MicroBlaze processor acts as a master for the Lite interface of the VDMA that is used
for register configuration.
TPG_0_VDMA
TPG_0_VDMA has two interfaces: one is the 32-bit streaming interface towards the DVI SCALAR block, and the other is the
64-bit AXI MM interface towards the axi_mm_video12 interconnect. The S2MM channel is enabled, and the
C_PRMRY_IS_ACLK_ASYNC parameter is set because clocks connected to the VDMA are of different frequencies. User
register slices on all channels are set to 8. The S2MM line buffer is set to 4096, and the burst length is set to 256. Write FIFO
delay in the interconnect settings are enabled with a FIFO delay of 512. The AXI MM and AXI Streaming interfaces operate
at 150 MHz, and the AXI-Lite interface operates at 100 MHz. The MicroBlaze processor acts as a master for the Lite
interface of the VDMA that is used for register configuration.
DVI_IN_1_VDMA
DVI_IN_1_VDMA has two interfaces: one is the 32-bit streaming interface towards the DVI2AXI block, and the other is a
64-bit AXI MM interface towards the axi_mm_video34 interconnect. The S2MM channel is enabled and the
C_PRMRY_IS_ACLK_ASYNC parameter is set because clocks connected to the VDMA are of different frequencies. User
register slices on all channels are set to 8. The S2MM line buffer is set to 4096, and the burst length is set to 256. Write FIFO
delay in the interconnect settings is enabled with a FIFO delay of 512. The AXI MM and AXI Streaming interfaces operate
at 150 MHz, and the AXI-Lite interface operates at 100 MHz. The MicroBlaze processor acts as a master for the Lite
interface of the VDMA that is used for register configuration.
SCALER_2_VDMA
SCALER_2_VDMA has four interfaces: two are 32-bit streaming interfaces towards the AXI SCALAR block, and the other
two are a 64-bit AXI MM interface towards the axi_mm_video34 interconnect. Both the S2MM and MM2S channels are
enabled, and the C_PRMRY_IS_ACLK_ASYNC parameter is set because clocks connected to VDMA are of different
frequencies. User register slices on all channels are set to 8. The S2MM line buffer is set to 4096, and the burst length is set
to 256. The MM2S line buffer is set to 256, and the burst length is set to 256. Write FIFO delay in the interconnect settings
is enabled with a FIFO delay of 512. The AXI MM and AXI Streaming interfaces operate at 150 MHz, and the AXI-Lite
interface operates at 100 MHz. The MicroBlaze processor acts as a master for the Lite interface of the VDMA that is used
for register configuration.
TPG_2_VDMA
TPG_2_VDMA has two interfaces: one is the 32-bit streaming interface towards the DVI SCALAR block, and the other is a
64-bit AXI MM interface towards the axi_mm_video34 interconnect. The S2MM channel is enabled, and the
C_PRMRY_IS_ACLK_ASYNC parameter is set because clocks connected to the VDMA are of different frequencies. User
register slices on all channels are set to 8. The S2MM line buffer is set to 4096, and the burst length is set to 256. Write FIFO
delay in the interconnect settings is enabled with a FIFO delay of 512. The AXI MM and AXI Streaming interfaces operate
at 150 MHz, and the AXI-Lite interface operates at 100 MHz. The MicroBlaze processor acts as a master for the Lite
interface of the VDMA that is used for register configuration.
CVC_DISPLAY
CVC_DISPLAY is a third-party display controller from Xylon. It has three interfaces: an AXI4-Lite interface slave connection
controlled by the MicroBlaze processor, an AXI MM interface towards the AXI MM interconnect, and a video output interface
towards the 24bit_16bit_ycbcr converter. The AXI MM data width is configured as 128. Configured for five layers, which
includes one background layer, the data width of all the layers is configured as 24 bits. User register slices on all channels
DS669 (v2.0) April 23, 2013
www.xilinx.com
Product Specification
24