DS669 Datasheet, PDF (21/28 Pages) Xilinx, Inc – AXI Interface Based

AXI Interface Based KC705 Embedded Kit MicroBlaze Processor Subsystem Data Sheet
Table 7: Clock Generator Configuration Settings (Cont’d)
Component
Frequency
(MHz)
Phase
Buffered
axi_tpg_dvi_1
• S_AXI_ACLK
100.000000
0
TRUE
• clk
150.000000
0
TRUE
DVI_1_2_AXI_SM
• fmc_hpc_dvidp_dvii_clk 150.000000
0
TRUE
• m_axi_s2mm_aclk
150.000000
0
TRUE
DVI_IN_1_VDMA
• s_axis_s2mm_aclk
150.000000
0
TRUE
• s_axi_lite_aclk
100.000000
0
TRUE
• m_axi_s2mm_aclk
150.000000
0
TRUE
SCALER_2_VDMA
• s_axis_s2mm_aclk
150.000000
0
TRUE
• m_axis_mm2s_aclk
150.000000
0
TRUE
• m_axi_s2mm_aclk
150.000000
0
TRUE
• m_AXI_MM2S_aclk
150.000000
0
TRUE
• s_axi_lite_aclk
100.000000
0
TRUE
SCALER_2
• m_AXI_MM2S_aclk
150.000000
0
TRUE
• m_axi_s2mm_aclk
150.000000
0
TRUE
axi_tpg_2
• S_AXI_ACLK
100.000000
0
TRUE
• clk
150.000000
0
TRUE
TPG_2_SCALE_2_AXI_SM
• fmc_hpc_dvidp_dvii_clk 150.000000
0
TRUE
• m_axi_s2mm_aclk
150.000000
0
TRUE
TPG_2_VDMA
• s_axis_s2mm_aclk
150.000000
0
TRUE
• s_axi_lite_aclk
100.000000
0
TRUE
• m_axi_s2mm_aclk
150.000000
0
TRUE
CVC_DISPLAY
• S_AXI_ACLK
100.000000
0
TRUE
• mclk
150.000000
0
TRUE
• vclk
150.000000
0
TRUE
dvi_24_to_16bit_ycbcr_0
• clk
150.000000
0
TRUE
Top-Level Output Clock Ports
• ddr_ck
800.000000
0
FALSE
• sd_clk
12.500000
0
FALSE
• hdmi_clk
150.000000
0
FALSE
DS669 (v2.0) April 23, 2013
www.xilinx.com
Product Specification
21