DS669 Datasheet, PDF (11/28 Pages) Xilinx, Inc – AXI Interface Based

AXI Interface Based KC705 Embedded Kit MicroBlaze Processor Subsystem Data Sheet
Note: The AXI interface slave connection clock on the axi_dma drives the axi_dma SG engine.
Ethernet Configuration
The axi_ethernet contains one AXI4-Lite interface slave connection and two AXI-Stream interfaces. The MicroBlaze
processor DP port is the master connected to the axi_ethernet slave connections through the shared mode on the axi4lite_0
interconnect. The two AXI-Stream interfaces are connected to the stream interface of the axi_dma IP.
The TEMAC is configured to support a GMII/MII PHY interface and contains internal 4 KB transmit and receive FIFOs. In
addition, TX and RX checksum offloading is enabled. On power-up or on reset, the on-board PHY is configured to operate
in GMII mode with the PHY address set to 00001. The TEMAC can run at 10 Mb/s, 100 Mb/s, or 1,000 Mb/s depending on
the network to which it is attached.
axi_xadc Configuration
The axi_xadc IP core consists of these major blocks:
• AXI4-Lite Interface Module
• XADC Core Logic
• XADC Hard Macro
The MicroBlaze processor DP port is connected as a master to the AXI-Lite interface of axi_xadc. Read and write
transactions at the AXI4 are translated into equivalent XADC core logic and XADC hard macro transactions by the AXI4-Lite
Interface Module.
Interrupt controller logic is included in the XADC core logic by setting the parameter C_INCLUDE_INTR = 1. The XADC hard
macro can be accessed via both the JTAG Test Access Port (TAP) and the axi_xadc IP core. When simultaneous access of
the XADC hard macro occurs, the JTAGLOCKED port can be asserted High by JTAG TAP. In this scenario, the axi_xadc IP
core is not allowed to do any read/write access from/to the DRP or FPGA logic.
logisdhc Configuration
This is a third-party IP core used for accessing SD cards on KC705 board. The logisdhc IP contains one AXI4-Lite interface
slave connection. The MicroBlaze processor DP port is the master connected to the logisdhc slave connections through the
shared mode on the axi4lite_0 interconnect. The SD base clock is 100 MHz. The clock generator lock output is connected
to the base clock input of the IP core to ensure that the clocks are stable well in advance.
Software Application and Board Support Package
This section provides a description of the software application and its associated board support package that is provided
with the system (Table 5).
Table 5: KC705 MicroBlaze Processor Subsystem Software Application
Software Platform
Software Application
Stand-alone
Board_Test_App_Console
Xilkernel
Board_Test_App_Webserver
See AXI Interface Based KC705 Embedded Kit MicroBlaze Processor Subsystem Software Tutorial [Ref 3] for more
information on how to execute and modify the software platform.
Stand-alone Platform
The stand-alone software platform is a simple, single-threaded environment that is used when an application accesses
processor functions directly.
DS669 (v2.0) April 23, 2013
www.xilinx.com
Product Specification
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