DS669 Datasheet, PDF (6/28 Pages) Xilinx, Inc – AXI Interface Based

AXI Interface Based KC705 Embedded Kit MicroBlaze Processor Subsystem Data Sheet
Table 2: System Clocks
Clock Signal
Source
Phased Locked Loop 0 (PLLE0)
CLK _P, CLK_N
External differential clock
freq_refclk
Internal PLL
mem_refclk
Internal PLL
sync_pulse
Internal PLL
clk_ref
Internal PLL
sys_clk_axilite_s
Internal MMCM
Mixed Mode Clock Manager 0 (MMCM0)
sys_clk_s
Internal MMCM
ethernet_clk
Internal clock gen
Frequency
(MHz)
200
800
800
50
200
100
150
125
Use
Input clock provided from the board.
Same as mem_refclk phase shifted by 337.5°.
Clock used for the memory controller.
0.0625 x freq_refclk. This signal must have a duty
cycle of 1/16 or 6.25%.
IDELAY clock for memory controller and TEMAC, also
used for AXI MM interface.
Low-speed slave clocks for axi4lite_0 interconnect.
Clock for Microblaze processor and instruction local
memory bus (ILMB)/data local memory bus (DLMB)
block RAM.
TEMAC GTX reference clock.
Clocks Generator Configuration
Clocks are generated by the clock generator. Based on the user’s clock configuration inputs, the clock generator determines
the correct configuration of the PLLs. The clock generator configuration wizard is invoked by selecting Hardware > Launch
Clock Wizard. The clock generator configuration settings are shown in Table 3.
Table 3: Clock Generator Configuration Settings
Component
Frequency
(MHz)
Phase
Input Clock
CLK
200.000000
Processor
microblaze_0
150.000000
0
Buses
axi4_0
200.000000
0
axi4lite_0
100.000000
0
Peripherals
proc_sys_reset_0
• Slowest_sync_clk
100.000000
0
Interrupt_Cntlr
• S_AXI_ACLK
100.000000
0
ilmb
• LMB_CLK
150.000000
0
dlmb
• LMB_CLK
150.000000
0
debug_module
• S_AXI_ACLK
100.000000
0
Dual_Timer_Counter
• S_AXI_ACLK
100.000000
0
Buffered
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
DS669 (v2.0) April 23, 2013
www.xilinx.com
Product Specification
6