DS586 Datasheet, PDF (9/21 Pages) Xilinx, Inc – LogiCORE IP XPS HWICAP

LogiCORE IP XPS HWICAP (v5.01a)
Table 8: Control Register Bit Definitions
Bit
Name
Access Reset Value
0 - 26
Reserved
N/A
’0’
27
Abort
Read/Write
’0’
28
SW_reset Read/Write
’0’
29
FIFO_clear Read/Write
’0’
30
Read
Read/Write
’0’
31
Write
Read/Write
’0’
Description
Reserved bits
’1’ = Aborts the read or write of the ICAP and clears the FIFOs
’1’ = Resets all the registers
’1’ = Clears the FIFOs
’1’ = Initiates readback of bitstream in to the Read FIFO
’1’ = Initiates writing of bitstream in to the ICAP
Status Register (SR)
This is a 9-bit read register as shown in Figure 6. The Status Register contains the ICAP status bits. The bit
definitions for the register are shown in Table 9. The offset and accessibility of this register from C_BASEADDR
value is as shown in Table 4.
X-Ref Target - Figure 6
Reserved
dalign in_abort_n
Done
0
22 23 24 25 26 27 28 29 30 31
Figure 6: Status Register (SR)
cfgerr_n rip
Always 1
DS586_06
Table 9: Status Register Bit Definitions
Bit
Name
Access
0 - 22
Reserved
N/A
23
cfgerr_n
Read
24
dalign
Read
25
rip
Read
26
in_abort_n
Read
27- 30
Always 1
Read
31
Done
Read
Reset Value
0
1
0
0
1
1
1
Description
Reserved bits
Configuration error
Data alignment, found syncword
Read back in progress
Super8 (Select MAP) abort
Always 1
XPS HWICAP done with configuration or read
Write FIFO Vacancy Register (WFV)
This is an 11-bit read register as shown in Figure 7. The write FIFO vacancy register indicates vacancy of the write
FIFO. The actual depth of the Write FIFO is one less than the C_WRITE_FIFO_DEPTH. The bit definitions for the
register are shown in Table 10. The offset and accessibility of this register from C_BASEADDR value is as shown in
Table 4.
X-Ref Target - Figure 7
WFV
0
20 21
31
Figure 7: Write FIFO Vacancy Register (WFV
DS586_07
DS586 June 22, 2011
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Product Specification