DS586 Datasheet, PDF (15/21 Pages) Xilinx, Inc – LogiCORE IP XPS HWICAP

LogiCORE IP XPS HWICAP (v5.01a)
Design Constraints
Timing Constraints on the clocks:
The core has two different clock domains: SPLB_Clk and ICAP_Clk. A timing ignore constraint should be added to
isolate these two clock domains. The constraints given below can be used with the XPS HWICAP core.
Period Constraints for Clock Nets
If the clock generator instantiated as below.
BEGIN clock_generator
---------------
---------------
PORT CLKOUT1 = PLB_Clk_125_0000MHz
PORT CLKOUT2 = ICAP_CLK_100MHz
---------------
---------------
END
Then the following constraints are required in the UCF.
NET "PLB_Clk_125_0000MHz" TNM = "PLBCLK_GRP";
NET "ICAP_CLK_100MHz" TNM = "ICAPCLK_GRP";
TIMESPEC TS_TIG0 = FROM "PLBCLK_GRP" TO "ICAPCLK_GRP" TIG;
TIMESPEC TS_TIG1 = FROM "ICAPCLK_GRP" TO "PLBCLK_GRP" TIG;
Timing Constraints on the ICAP interface:
If the Internal Configuration Access Port (ICAP) is used as the configuration port for partially reconfiguring the
FPGA, timing constraints can be very useful to understand the potential performance of this interface. It is
important to understand that the paths to the ICAP and from the ICAP are not covered by PERIOD constraints. The
ICAP inputs and outputs are not considered synchronous by TRCE. This means that the inputs to and the outputs
from the ICAP must be constrained using the exception constraint: NET MAXDELAY.
The following MAXDELAY constraints are required in the UCF:
NET "xps_hwicap_0/xps_hwicap_0/HWICAP_CTRL_I/icap_statemachine_I1/Icap_datain<*>" MAXDELAY = 2 ns;
NET "xps_hwicap_0/xps_hwicap_0/HWICAP_CTRL_I/icap_statemachine_I1/Icap_ce" MAXDELAY = 2 ns;
NET "xps_hwicap_0/xps_hwicap_0/HWICAP_CTRL_I/icap_statemachine_I1/Icap_we" MAXDELAY = 2 ns;
The asterisk represents the entire bus (that is, 0, 1, 2, …). The NET MAXDELAY constraint constrains only the net
delay. It does not take the setup time or clock-to-out time into consideration. The ICAP component cannot be added
to time groups because it is not considered a synchronous element. Therefore, the ICAP cannot be made a
synchronous component by use of a TPSYNC constraint. The ICAP component is a special type of component
DS586 June 22, 2011
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Product Specification