DS586 Datasheet, PDF (13/21 Pages) Xilinx, Inc – LogiCORE IP XPS HWICAP

LogiCORE IP XPS HWICAP (v5.01a)
• Abort
• Write in to the Control Register (CR) to initiates the read or write of bit-stream. The CR register determines
the direction of the data transfer. Writing "0x00000001" in to the Control Register (CR) initiates the
configuration. Writing "0x00000002" in to the Control Register (CR) initiates the read.
• Write the bit-stream in to the Write FIFO Register (WF) to configure. Get the bit-stream from the Read FIFO
Register (RF) to read.
• Write ’1’ in to the 27th bit of the Control Register (CR) to initiates abort
• Done bit in the Status Register (SR) indicates whether the ICAP interface is busy with writing/reading
data from/to the ICAP bus. It doesn’t not indicate that the read/configuration with ICAP is completed
successfully.
• Hardware clears the Control Register (CR) bits after the successful completion of the abort-on read or
abort-on configuration or normal abort
• Software should not initiate another read or configuration to ICAP until the read or configuration bit in the
Control Register (CR) is cleared
Timing Diagrams
The following timing diagram Figure 12, Figure 13 and Figure 14 shows read and write cycles of XPS HWICAP core
for Virtex-4, Virtex5, Virtex-6 and Spartan-6 family of FPGA devices.
X-Ref Target - Figure 12
cycle_number 1
2
3
4
5
6
7
8
9
10 11
icap_clk
rnc[7:0]
"00"
"10"
"00"
size_reg 0
3
2
1
0
rdfifo_wren
rdfifo_datain[7:0]
D0
D1
D2
icap_dataout[7:0]
D0
D1
D2
icap_ce
icap_we
icap_busy
send_done
reset_cr
DS586_12
Figure 12: Read Cycle - Virtex-4, Virtex5 and Virtex-6 Devices
X-Ref Target - Figure 13
cycle_number 1
2
3
4
5
6
7
8
9
icap_clk
rnc[7:0]
"00"
"10"
size_reg 0
3
2
1
0
rdfifo_wren
rdfifo_datain[7:0]
D0
D1
D2
icap_dataout[7:0]
D0
D1
D2
icap_ce
icap_we
icap_busy
send_done
reset_cr
Figure 13: Read Cycle - Spartan -6 Devices
10
11
"00"
DS586_13
DS586 June 22, 2011
www.xilinx.com
13
Product Specification