DS586 Datasheet, PDF (14/21 Pages) Xilinx, Inc – LogiCORE IP XPS HWICAP

LogiCORE IP XPS HWICAP (v5.01a)
X-Ref Target - Figure 14
cycle_number 1
2
3
4
5
6
7
icap_clk
rnc[7:0]
"00"
"01"
wrfifo_empty
wrfifo_rden
wrfifo_dataout[7:0]
D0
D1
D2
icap_datain[7:0]
D0
D1
D2
icap_ce
icap_we
icap_busy
send_done
reset_cr
Figure 14: Write Cycle
8
9
10
"00"
DS586_14
Limitations
A frame is the smallest granularity in which the FPGA allows configuration data to be read and written. A
configuration frame is a collection of bits that is 1 bit wide and spans the full column of the FPGA. Configuration
frames in the CLB space also contain IOB configuration data at the top and bottom, which configure the IOBs at the
top and bottom of the FPGA. A single column of CLBs contains multiple configuration frames.
Although a single CLB LUT or flip-flop can be modified, the underlying mechanism requires that the full column be
read into Block RAM. This implies that other logic in the same column can be modified. In most cases, this effect can
be ignored. When the frame is written back to the configuration memory the sections of the column that were not
modified are written with the same data. Because the FPGA memory cells have glitch less transitions, when
rewritten, the unmodified logic will continue to operate unaffected.
Two exceptions to this rule exist: when LUTs are configured in Shift Register Mode or as a RAM. If a LUT is
modified or just read back in a column that also has a LUT RAM or LUT shift register, then the LUT or shift register
will be interrupted and it will lose its state. To resolve the problem, the LUT shift registers and LUT RAMs should
be placed in columns that are not read back or modified. If the LUT RAMs or shift register in a column do not
change state during the read back or modification, then they will maintain their state.
Important Notes:
1. The HWICAP core uses the ICAP found inside Virtex-4, Virtex-5, Virtex-6 and Spartan-6 devices. The ICAP
port interface is similar to the SelectMAP interface, but is accessible from general interconnects rather than the
device pins. The JTAG or “Boundary Scan” configuration mode pin setting (M2:M0 = 101) will disable the ICAP
interface. Therefore, when using the HWICAP core, another mode pin setting must be used. If JTAG will be
used as the primary configuration method, another mode pin setting must be selected to avoid disabling the
ICAP interface. JTAG configuration will remain available because it overrides other means of configuration,
and the HWICAP core will function as intended. Besides being disabled by the Boundary Scan mode pin
setting, the ICAP will also be disabled if the persist bit in the device configuration logic’s control register is set.
When using bitgen, the Persist option must be set to No, which is the default. This option is generally specified
in the bitgen.ut file in the etc. subdirectory of the EDK project. The maximum frequency of operation for ICAP
on Virtex-4, Virtex-5 and Virtex-6 is 100 MHz. In case of Spartan-6 the maximum frequency of operation for
ICAP is 20 MHz.
2. In case of If Virtex-4, Virtex-5 and Virtex-6 the PLB operates at less than 100MHz then the ICAP clock must be
given frequency equivalent to PLB clock frequency. I.e If the PLB frequency is 90 MHz, then ICAP clock also
should be 90 MHz. Suggested to derive two independent clocks from clock generator even the frequencies are
same. If the PLB operates greater than 100 MHz, then the ICAP clock must be fixed to 100 MHz.
3. In case of Spartan-6 the ICAP clock must be connected to 20 MHz.
DS586 June 22, 2011
www.xilinx.com
14
Product Specification