DS586 Datasheet, PDF (3/21 Pages) Xilinx, Inc – LogiCORE IP XPS HWICAP

LogiCORE IP XPS HWICAP (v5.01a)
IPIC_IF Module
IPIC_IF module incorporates logic to acknowledge the write and read transactions initiated by the plbv46 slave
burst module to write/read the HWICAP module registers and FIFOs.
HWICAP Module
The HWICAP module provides the interface to the Internal Configuration Access Port (ICAP). It has a write FIFO,
which will store the configuration locally. The Processor writes the configuration in to the write FIFO.
Simultaneously the data stored in the write FIFO transferred to the ICAP. Processor can read the configuration from
the ICAP, which will be stored in side the read FIFO. FIFOs are required as the rate of data flow from the processor
interface is different from ICAP interface. FIFO depth can be parameterizable using the generics
C_WRITE_FIFO_DEPTH, C_READ_FIFO_DEPTH.
The FIFO data width is based on the device family. For Virtex-4, Virtex-5, Virtex-6 it is 32 bit; for Spartan-6 it is 16 bit
and 8 bit for Spartan-3A.
Note: In case of Virtex-4, Virtex-5 and Virtex-6: If the SPLB_Clk is greater than 100 MHz, the ICAP_Clk should be connected
to 100 MHz. If the SPLB_Clk is less than or equal to 100 MHz, the ICAP_Clk should be connected to the frequency equivalent
to SPLB_clk frequency.
Note: In case of Spartan-6 the maximum frequency of operation of ICAP is 20 MHz. The ICAP_Clk must be connected to a
frequency less than or equal to 20 MHz.
I/O Signals
The I/O signals are listed and described in Table 1.
Table 1: I/O Signals
Port
Signal Name
Interface I/O
Initial
State
Description
ICAP Interface Signals
P1 ICAP_Clk ⁽¹⁾
ICAP
I
-
ICAP clock
PLB Bus Request and Qualifier Signals
P2 SPLB_Clk
PLB
I
-
PLB main bus clock
P3 SPLB_Rst
PLB
I
-
PLB main bus reset
P4 PLB_ABus(0 : C_SPLB_AWIDTH-1)
PLB
I
-
PLB address bus
P5 PLB_PAValid
PLB
I
-
PLB primary address valid indicator
P6
PLB_masterID(0 :
C_SPLB_MID_WIDTH - 1)
PLB
I
-
PLB current master identifier
P7 PLB_RNW
PLB
I
-
PLB read not write
P8 PLB_BE[0 : (C_SPLB_DWIDTH/8 - 1) PLB
I
-
PLB byte enables
P9 PLB_wrBurst
PLB
I
-
PLB write burst
P10 PLB_rdBurst
PLB
I
-
PLB read burst
P11 PLB_size(0 : 3)
PLB
I
-
PLB transfer size
P12 PLB_type(0 : 2)
PLB
I
-
PLB transfer type
P13
PLB_wrDBus(0 : C_SPLB_DWIDTH -
1)
PLB
I
-
PLB write data bus
DS586 June 22, 2011
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