DS586 Datasheet, PDF (12/21 Pages) Xilinx, Inc – LogiCORE IP XPS HWICAP

LogiCORE IP XPS HWICAP (v5.01a)
Table 14: IP Interrupt Enable Register Bit Definitions
Bit(s)
Name
Access Reset Value
Description
0 - 27
28
Undefined
RFULLE
N/A
R/W^<RD
Red>(1)
N/A
Undefined.
’0’
Read FIFO full interrupt enable
29
WEMTYE
R/W^<RD
Red>(1)
’0’
Write FIFO empty interrupt enable
30
RDPE
R/W^<RD
Red>(1)
’0’
Read FIFO occupancy greater than half of its size interrupt
enable
31
WRPE
R/W^<RD
Red>(1)
’0’
Write FIFO occupancy less than half of its size interrupt enable
Notes:
1. Writing ’1’ to this bit will enable the particular interrupt. Writing ’0’ to this bit will disable the particular interrupt.
Abort
An Abort is an interruption in the configuration or read-back sequence occurring when the state of icap_we
changes while icap_ce is asserted. During a configuration Abort, internal status is driven onto the icap_dout[7:4]
pins over the next four clock cycles. The other icap_dout pins are always high. After the Abort sequence finishes,
the user can re-synchronize the configuration logic and resume configuration. Abort enable the user to know the
status of the ICAP during the configuration or reading the configuration.
Software Support
Documentation for the associated software drivers for this hardware module are also available in EDK.
User Application Hints
The use of the XPS HWICAP is outlined in the steps below.
• Read or Configuration (write)
• Write the bit-stream in to the Write FIFO Register (WF) to configure. Get the bit-stream from the Read FIFO
Register (RF) to read.
• Write in to the Control Register (CR) initiates the read or write of bit-stream. The CR register determines
the direction of the data transfer. Writing "0x00000001" in to the Control Register (CR) initiates the
configuration. Writing "0x00000002" in to the Control Register (CR) initiates the read.
• Done bit in the Status Register (SR) indicates whether the ICAP interface is busy with writing/reading
data from/to the ICAP bus. It doesn’t not indicate that the read/configuration with ICAP is completed
successfully
• Hardware clears the Control Register (CR) bits after the successful completion of the read or configuration
• Software should not initiate another read or configuration to ICAP until the read or configuration bit in the
Control Register (CR) is cleared
DS586 June 22, 2011
www.xilinx.com
12
Product Specification