DS586 Datasheet, PDF (4/21 Pages) Xilinx, Inc – LogiCORE IP XPS HWICAP

LogiCORE IP XPS HWICAP (v5.01a)
Table 1: I/O Signals (Cont’d)
Port
Signal Name
P14 PLB_MSize(0:1)
P15 Sl_addrAck
P16 Sl_SSize(0:1)
P17 Sl_wait
P18 Sl_rearbitrate
P19 Sl_wrDack
P20 Sl_wrComp
P21 Sl_wrBTerm
P22 Sl_rdBus(0:C_SPLB_DWIDTH - 1)
P23 Sl_rdDAck
P24 Sl_rdComp
P25 Sl_rdBTerm
P26 Sl_rdWdAddr(0:3)
P27
Sl_MBusy(0:C_SPLB_NUM_
MASTERS-1)
P28
Sl_MWrErr(0:C_SPLB_NUM_
MASTERS-1)
P29
Sl_MRdErr(0:C_SPLB_NUM_
MASTERS-1)
P30 PLB_UABus(0:C_SPLB_AWIDTH-1)
P31 PLB_SAValid
P32 PLB_rdPrim
P33 PLB_wrPrim
P34 PLB_abort
P35 PLB_busLock
P36 PLB_TAttribute(0:15)
P37 PLB_lockerr
P38 PLB_wrPendReq
P39 PLB_rdPendReq
P40 PLB_rdPendPri(0:1)
P41 PLB_wrPendPri(0,1)
P42 PLB_reqPri(0:1)
P43
Sl_MIRQ(0:C_SPLB_NUM_MASTER
S-1)
Interface I/O
Initial
State
PLB
I
-
PLB
O
0
PLB
O
0
PLB
O
0
PLB
O
0
PLB
O
0
PLB
O
0
PLB
O
0
PLB
O
0
PLB
O
0
PLB
O
0
PLB
O
0
PLB
O
0
PLB
O
0
PLB
O
0
PLB
O
0
Unused PLB signals
PLB
I
-
PLB
I
-
PLB
I
-
PLB
I
-
PLB
I
-
PLB
I
-
PLB
I
-
PLB
I
-
PLB
I
-
PLB
I
-
PLB
I
-
PLB
I
-
PLB
I
-
PLB
O
0
Description
PLB data bus width indicator
Slave address acknowledge
Slave data bus size
Slave wait indicator
Slave rearbitrate bus indicator
Slave write data acknowledge
Slave write transfer complete indicator
Slave terminate read burst transfer
Slave read data bus
Slave read data acknowledge
Slave read transfer complete indicator
Slave terminate read burst transfer
Slave read word address
Slave busy indicator
Slave write error indicator
Slave read error indicator
PLB upper address bits
PLB secondary address valid
PLB secondary to primary read request
indicator
PLB secondary to primary write request
indicator
PLB abort bus request
PLB bus lock
PLB transfer attribute
PLB lock error
PLB pending bus write request
PLB pending bus read request
PLB pending read request priority
PLB pending write request priority
PLB current request priority
Master interrupt request
DS586 June 22, 2011
www.xilinx.com
4
Product Specification