DS586 Datasheet, PDF (7/21 Pages) Xilinx, Inc – LogiCORE IP XPS HWICAP

LogiCORE IP XPS HWICAP (v5.01a)
Table 3: Parameter-Port Dependencies (Cont’d)
Generic
or Port
Name
Affects
P27
Sl_MBusy[0:C_SPLB_NUM_
MASTERS - 1]
-
P28
Sl_MWrErr[0:C_SPLB_NUM_
MASTERS - 1]
-
P29
Sl_MRdErr[0:C_SPLB_NUM_
MASTERS - 1]
-
P43
Sl_MIRQ(0:C_SPLB_NUM_
MASTERS-1)
-
Depends
Relationship Description
G7 Width varies with the number of masters on the PLB
G7 Width varies with the number of masters on the PLB
G7 Width varies with the number of masters on the PLB
G7 Width varies with the number of masters on the PLB
Register Definition
The internal registers of the XPS HWICAP are offset from the base address C_BASEADDR. The XPS HWICAP
internal register set is described in Table 4.
Table 4: XPS HWICAP Registers
Register Name
C_BASEADDR + Address
Access
Global Interrupt Enable Register (GIE)
C_BASEADDR + 0x01C
Read/Write
IP Interrupt Enable Register (IPIER)
C_BASEADDR + 0x020
Read/Write
IP Interrupt Enable Register (IPIER)
C_BASEADDR + 0x028
Read/Write
Write FIFO Register (WF)
C_BASEADDR + 0x100
Write
Read FIFO Register (RF)
C_BASEADDR + 0x104
Read
Size Register (SZ)
C_BASEADDR + 0x108
Write
Control Register (CR)
C_BASEADDR + 0x10C
Read/Write
Status Register (SR)
C_BASEADDR + 0x110
Read
Write FIFO Vacancy Register (WFV)
C_BASEADDR + 0x114
Read
Read FIFO Occupancy Register (RFO)
C_BASEADDR + 0x118
Read
Write FIFO Register (WF)
This is a 32-bit Write FIFO as shown in Figure 2. The bit definitions for the Write FIFO are shown in Table 5. The
offset and accessibility of this register from C_BASEADDR value is as shown in Table 4.
X-Ref Target - Figure 2
WF
0
Table 5: Write FIFO Bit Definitions
Bit
Name
Access
0 - 31
WF
Write
Figure 2: Write FIFO (WF)
Reset Value
0
31
DS586_02
Description
Data written into the FIFO
DS586 June 22, 2011
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Product Specification