DS586 Datasheet, PDF (5/21 Pages) Xilinx, Inc – LogiCORE IP XPS HWICAP

LogiCORE IP XPS HWICAP (v5.01a)
Table 1: I/O Signals (Cont’d)
Port
Signal Name
Interface I/O
Initial
State
Description
p44 IP2INTC_Irpt
System Signals
PLB
O
0
XPS HWICAP Interrupt
Notes:
1. ICAP_Clk must be less than or equal to 20 MHz or 12 MHz or 4 MHzin case of Spartan-6 FPGAs. The Spartan-6 LX4 to LX75/T
devices have a limiting frequency of 20 MHz. The Spartan-6 LX100/T to LX150/T devices have a limiting frequency of 12 MHz. The
Spartan-6 Low Power devices have a limiting frequency of 4 MHz. The Virtex-6 devices have a limiting frequency of maximum 100
MHz on ICAP_Clk.
Design Parameters
To allow the user to create a core that is uniquely tailored for the user’s system, certain features are parameterizable
in the design. This allows the user to have a design that utilizes only the resources required by the system and runs
at the best possible performance. The features that are parameterizable in the core are as shown in Table 2.
Table 2: Design Parameters
Generic
Parameter Description
Parameter Name
Allowable Values
Default
Value
VHDL
Type
PLB Parameters
G1 XPS HWICAP Base Address C_BASEADDR
Valid Word Aligned Address⁽¹⁾
None⁽²⁾
std_logic_v
ector
G2 XPS HWICAP High Address C_HIGHADDR
C_HIGHADDR
-C_BASEADDR must be a
power of 2 >= to
C_BASEADDR+1FF⁽¹⁾
None⁽²⁾
std_logic_v
ector
G3 PLB Data Bus Width
C_SPLB_DWIDTH 32, 64, 128
32
integer
G4 PLB Address Bus Width
C_SPLB_AWIDTH 32
32
integer
G5
PLB Point-to-Point or shared bus
topology
C_SPLB_P2P
0 : Shared bus topology
1 : Reserved
0
integer
G6 PLB master ID bus width
C_SPLB_MID_
WIDTH
log₂(C_SPLB_NUM_MASTE
RS) with a minimum value of 1
3
integer
G7 Number of PLB masters
C_SPLB_NUM_
MASTERS
1 - 16
8
integer
G8 Width of slave data bus
C_SPLB_NATIVE_
DWIDTH
32
32
integer
G9
Width of the smallest master that
will be interacting with this slave
C_SPLB_SMALLEST
_MASTER
32, 64, 128
32
integer
G10 Write FIFO depth
C_WRITE_FIFO_
DEPTH⁽³⁾⁽⁶⁾
64, 128, 256, 512,1024
64
integer
G11 Read FIFO depth
C_READ_FIFO_
DEPTH⁽³⁾⁽⁶⁾
128, 256
128
integer
G12 Select FIFO type⁽⁴⁾
C_BRAM_SRL_
FIFO_TYPE
0,1
1
integer
System Parameters
DS586 June 22, 2011
www.xilinx.com
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Product Specification