DS586 Datasheet, PDF (11/21 Pages) Xilinx, Inc – LogiCORE IP XPS HWICAP

LogiCORE IP XPS HWICAP (v5.01a)
IP Interrupt Status Register (IPISR)
Four unique interrupt conditions are possible in HWICAP core. The Interrupt Controller has a register that can
enable each interrupt independently. Bit assignment in the Interrupt register for a 32-bit data bus is shown in
Figure 10 and described in Table 13. The interrupt register is a read/toggle on write register and by writing a ’1’ to
a bit position within the register causes the corresponding bit position in the register to ’toggle’. All register bits are
cleared upon reset.
X-Ref Target - Figure 10
WEMTY WRP
0
27 28 29 30 31
Figure 10: IP Interrupt Status Register (IPISR)
RFULL
RDP
DS586_10
Table 13: IP Interrupt Status Register Bit Definitions
Bit(s)
Name
Access Reset Value
Description
0 - 27
28
Undefined
RFULL
N/A
R/TOW^<RD
Red><SP
Superscript>(1)
N/A
Undefined
’0’
Read FIFO full
R/TOW^<RD
29
WEMTY
Red><SP
’0’
Write FIFO empty
Superscript>(1)
30
RDP
R/TOW^<RD
Red><SP
Superscript>(1)
’0’
Interrupt set and remains set if the read FIFO occupancy is greater
than half of the read FIFO size
31
WRP
R/TOW^<RD
Red><SP
Superscript>(1)
’0’
Interrupt set and remains set if the write FIFO occupancy is less
than half of the write FIFO size
Notes:
1. TOW = Toggle On Write. Writing a ’1’ to a bit position within the register causes the corresponding bit position in the register to
toggle.
IP Interrupt Enable Register (IPIER)
The IPIER has an enable bit for each defined bit of the IPISR as shown in Figure 11 and described in Table 14. All bits
are cleared upon reset.
X-Ref Target - Figure 11
WEMTYE WRPE
0
27 28 29 30 31
Figure 11: IP Interrupt Enable Register (IPIER)
RFULLE RDPE
DS586_11
DS586 June 22, 2011
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