DS586 Datasheet, PDF (6/21 Pages) Xilinx, Inc – LogiCORE IP XPS HWICAP

LogiCORE IP XPS HWICAP (v5.01a)
Table 2: Design Parameters (Cont’d)
Generic
Parameter Description
Parameter Name
Allowable Values
G12 XILINX FPGA Family
G13 Simulation⁽⁵⁾
C_FAMILY
C_SIMULATION
spartan3, aspartan3,
spartan3an, spartan3a,
spartan3e, spartan3adsp,
aspartan3e, aspartan3a,
aspartan3adsp, virtex4,
virtex5,virtex5fx, qvirtex4,
qrvirtex4, spartan6,
aspartan6, virtex6.virtex6cx
1: FIFO Model
2: UNISIM Model
Default
Value
spartan3
2
VHDL
Type
string
integer
Notes:
1. Address range specified by C_BASEADDR and C_HIGHADDR. C_BASEADDR must be a multiple of the range, where the range
is C_HIGHADDR - C_BASEADDR +1 and must be a power of 2. For example, C_BASEADDR = 0x10000000, C_HIGHADDR =
0x100001FF.
2. No default value will be specified to insure that the actual value is set, i.e. if the value is not set, a compiler error will be generated.
3. This parameter must be set to 256 if the C_FAMILY = virtex6/spartan6, as the frame size in virtex6/spartan6 family is 162 bytes
4. The parameter C_BRAM_SRL_FIFO_TYPE selects the FIFO type to be BRAM (1) or Distributed RAM (0)
5. The parameter C_SIMULATION must be set to 2 for simulations using the ICAP unisim model.
6. The Actual depth of the Write/Read FIFO is one less than the parameter defining the depth of the FIFOs (for examplet, either
C_WRITE_FIFO_DEPTH or C_READ_FIFO_DEPTH)
Parameter - Port Dependencies
The dependencies between the XPS HWICAP core design parameters and I/O signals are described in Table 3. In
addition, when certain features are parameterized out of the design, the related logic will no longer be a part of the
design. The unused input signals and related output signals are set to a specified value.
Table 3: Parameter-Port Dependencies
Generic
or Port
Name
Affects Depends
Relationship Description
Design Parameters
G3 C_SPLB_DWIDTH
P8, P13, P22
-
Affects the size of the PLB data bus
G4 C_SPLB_AWIDTH
P4, P30
-
Affects the size of the PLB address bus
G6 C_SPLB_MID_WIDTH
P6
G9 Affects the width of the PLB master ID
G7 C_SPLB_NUM_MASTERS
P27, P28,
P29, P43
-
Identify the specific master on the PLB
I/O Signals
P4
PLB_ABus[0:C_SPLB_
AWIDTH - 1]
-
G4 Width varies with the size of the PLB address bus
P6
PLB_masterID[0:
C_SPLB_MID_WIDTH - 1]
-
G6
Width varies with the size of the number of masters
on the PLB
P8
PLB_BE[0:[C_SPLB_
DWIDTH/8] - 1]
-
G3 Width varies with the size of the PLB data bus
P13
PLB_wrDBus[0:C_SPLB_
DWIDTH - 1]
-
G3 Width varies with the size of the PLB data bus
P22
Sl_rdBus[0:C_SPLB_
DWIDTH - 1]
-
G3 Width varies with the size of the PLB data bus
DS586 June 22, 2011
www.xilinx.com
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Product Specification