DS586 Datasheet, PDF (10/21 Pages) Xilinx, Inc – LogiCORE IP XPS HWICAP

LogiCORE IP XPS HWICAP (v5.01a)
Table 10: Write FIFO Vacancy Register Bit Definitions
Bit
Name
Access Reset Value
0 - 21 Reserved
NA
-
22 - 31
WFV
Read
0
Description
Reserved
Write FIFO Vacancy
Read FIFO Occupancy Register (RFO)
This is an 8-bit read register as shown in Figure 8. The read FIFO occupancy register indicates occupancy of the read
FIFO. The actual depth of the Write FIFO is one less than the C_WRITE_FIFO_DEPTH. The bit definitions for the
register are shown in Table 11. The offset and accessibility of this register from C_BASEADDR value is as shown in
Table 4.
X-Ref Target - Figure 8
RFO
0
23 24
Figure 8: Read FIFO Occupancy Register (RFO)
Table 11: Read FIFO Occupancy Register Bit Definitions
Bit
Name
Access
Reset Value
Description
0 - 24
Reserved
N/A
-
Reserved
25 - 31
RFO
Read
0
Read FIFO Occupancy
31
DS586_08
Interrupt Descriptions
The interrupt signals generated by the XPS HWICAP are managed by the Interrupt Service Controller (ISC). This
unit provides many of the features commonly provided for interrupt handling. Please refer to the Processor IP
Reference Guide under Part 1 for a complete description of the GIE, IPISR and IPIER. The XPS XPSHWICAP has four
unique interrupts that are sent to the CPU.
Global Interrupt Enable Register (GIE)
The Global Interrupt Enable Register (GIE) is used to globally enable the final interrupt output from the Interrupt
Controller as shown in Figure 9 and described in Table 12. This bit is a read/write bit and is cleared upon reset.
X-Ref Target - Figure 9
GIE
Reserved
01
Figure 9: Global Interrupt Enable Register (GIER)
Table 12: Global Interrupt Enable Register Bit Definitions
Bit(s)
Name
Access
Reset Value
0
GIE
R/W
’0’
’0’ = Disabled
’1’ = Enabled
1 - 31
Reserved
N/A
N/A
Reserved
Description
31
DS586_09
DS586 June 22, 2011
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Product Specification