DS586 Datasheet, PDF (2/21 Pages) Xilinx, Inc – LogiCORE IP XPS HWICAP

LogiCORE IP XPS HWICAP (v5.01a)
Functional Description
The XPS HWICAP controller provides the interface necessary to transfer bitstreams to and from the ICAP. The CPU
bursts the required bitstream data directly from main memory. Incoming data is stored within a Write FIFO, from
where it can be fed to the ICAP. The XPS HWICAP also provides for read back of configuration resource states. In
this case, the frames are read back into the Read FIFO one at a time and the CPU will then be able to read the frame
data directly from the Read FIFO.
Sample Applications
• A DSP system, like software defined radio, where the filters and algorithms are modified at run time to receive
and transmit at variable frequencies, or adapt to variable protocols.
• A debug system where trigger conditions are implemented as comparator circuits and modified at run time to
enable variable trigger conditions. The system can also have counters to measure the amount of data sampled.
The final counts of the counters can be modified to vary the amounts of data sampled.
• A crossbar switch where the fundamental switches are implemented using multiplexers in the routing fabric.
The crossbar connections are reconfigured at run time by reconfiguring the routing multiplexers
The XPS HWICAP top-level block diagram is shown in Figure 1.
X-Ref Target - Figure 1
XPS HWICAP Core
PLB Inteface
PLBv46 Slave Burst Inteface
HWICAP
Interrupt Control Unit
Read Write
Asynchrounous FIFOs
SZ Register
CR Register
SZ Register
WFV Register
RFO Register
ICAP State
Machine
ICAP
IPIC_IF
ICAP_Clk
IP2INTC_Iprt
DS586_01
Figure 1: Top Level Block Diagram for the XPS HWICAP Core
PLBV46 Slave Burst Module
PLBV46 Salve Burst Module provides the bidirectional interface between HWICAP core and the PLB. The base
element of the PLB Interface Module is slave attachment with burst support, which provides the basic functionality
of PLB slave operation.
DS586 June 22, 2011
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Product Specification