DS586 Datasheet, PDF (20/21 Pages) Xilinx, Inc – LogiCORE IP XPS HWICAP

LogiCORE IP XPS HWICAP (v5.01a)
The target FPGA was then filled with logic to drive the LUT and BRAM utilization to approximately 70% and the
I/O utilization to approximately 80%. Using the default tool options and the slowest speed grade for the target
FPGA, the resulting target F_MAX numbers are shown in Table 19.
Table 19: XPS HWICAP Core System Performance
Target FPGA
V4FX60 -10
Target F_MAX (MHz)
100
V5FX70T -1
125
V6LX130t - 1
150
S6LX45t - 2
100
The target F_MAX is influenced by the exact system and is provided for guidance. It is not a guaranteed value across
all systems.
Reference Documents
The following document contains reference information important to understanding the XPS HWICAP core:
1. IBM CoreConnect 128-Bit Processor Local Bus, Architectural Specification (v4.6)
2. PLBv46_Slave_Burst_v1_00_a (DS562) Design Specification
Support
Xilinx provides technical support for this LogiCORE product when used as described in the product
documentation. Xilinx cannot guarantee timing, functionality, or support of product if implemented in devices that
are not defined in the documentation, if customized beyond that allowed in the product documentation, or if
changes are made to any section of the design labeled DO NOT MODIFY.
Ordering Information
This Xilinx LogiCORE IP module is provided at no additional cost with the Xilinx ISE Design Suite Embedded
Edition software under the terms of the Xilinx End User License. The core is generated using the Xilinx ISE
Embedded Edition software (EDK).
Information about this and other Xilinx LogiCORE IP modules is available at the Xilinx Intellectual Property page.
For information on pricing and availability of other Xilinx LogiCORE modules and software, please contact your
local Xilinx sales representative.
DS586 June 22, 2011
www.xilinx.com
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Product Specification