DS586 Datasheet, PDF (8/21 Pages) Xilinx, Inc – LogiCORE IP XPS HWICAP

LogiCORE IP XPS HWICAP (v5.01a)
Read FIFO Register (RF)
This is a 32-bit Read FIFO as shown in Figure 3. The bit definitions for the Read FIFO are shown in Table 6. The
offset and accessibility of this register from C_BASEADDR value is as shown in Table 4.
X-Ref Target - Figure 3
RF
0
Table 6: Read FIFO Bit Definitions
Bit
Name
Access
0 - 31
RF
Read
Figure 3: Read FIFO (RF)
Reset Value
0
31
DS586_03
Description
Data read from the FIFO
Size Register (SZ)
This is a 12-bit write register as shown in Figure 4. The SZ register determines the number of words to be transferred
from the ICAP to the read FIFO. The bit definitions for the register are shown in Table 7. The offset and accessibility
of this register from C_BASEADDR value is as shown in Table 4.
X-Ref Target - Figure 4
Figure 4: Size Register (SZ)
Table 7: Size Register Bit Definitions
Bit
Name
Access Reset Value
0 - 19
Reserved
N/A
0
20 - 31
Size
Write
0
Description
Reserved bits
Number of words to be transferred from the ICAP to the FIFO
Control Register (CR)
This is a 4-bit write register as shown in Figure 5. The CR register determines the direction of the data transfer. It
controls whether a configuration or read back takes place. Writing to this register initiates the transfer. The bit
definitions for the register are shown in Table 8. The offset and accessibility of this register from C_BASEADDR
value is as shown in Table 4.
X-Ref Target - Figure 5
Reserved
Abort
Write
FIFO_clear
0
27 28 29 30 31
Figure 5: Control Register (CR)
SW_reset Read
DS586_05
DS586 June 22, 2011
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Product Specification