DS572 Datasheet, PDF (9/26 Pages) Xilinx, Inc – LogiCORE IP XPS Interrupt

LogiCORE IP XPS Interrupt Controller (v2.01a)
Table 3: XPS INTC Parameter-Port Dependencies (Cont’d)
Generic
or port
Name
Affects Depends
G11 C_NUM_INTR_INPUTS
P43
G9
P5
PLB_masterID[0 :
C_SPLB_NUM_MASTERS - 1]
P7
PLB_BE[0 : (C_SPLB_
DWIDTH/8) - 1]
P10
PLB_wrDBus
[0 : C_SPLB_DWIDTH - 1]
P33 Sl_rdDBus[0 : C_SPLB_DWIDTH - 1]
P36
Sl_MBusy[0 :
C_SPLB_NUM_MASTERS - 1]
P37
Sl_MWrErr[0 :
C_SPLB_NUM_MASTERS - 1]
P38
Sl_MRdErr[0 :
C_SPLB_NUM_MASTERS - 1]
P42
Sl_MIRQ[0 :
C_SPLB_NUM_MASTERS - 1]
P43 Intr[(C_NUM_INTR_INPUTS-1) : 0]
I/O Signals
-
G7
-
G5
-
G5
-
G5
-
G7
-
G7
-
G7
-
G7
-
G11
Relationship Description
Affects number of bits in Intr.
C_NUM_INTR_INPUTS <=
C_SPLB_NATIVE_DWIDTH
Width varies with the parameter
C_SPLB_NUM_MASTERS
Width varies with the parameter
C_SPLB_DWIDTH
Width varies with the parameter
C_SPLB_DWIDTH
Width varies with the parameter
C_SPLB_DWIDTH
Width varies with the parameter
C_SPLB_NUM_MASTERS
Width varies with the parameter
C_SPLB_NUM_MASTERS
Width varies with the parameter
C_SPLB_NUM_MASTERS
Width varies with the parameter
C_SPLB_NUM_MASTERS
Width varies with the parameter
C_NUM_INTR_INPUTS
Programming Model
Register Data Types and Organization
All XPS INTC registers are accessed through the PLB interface. The base address for these registers is provided by
the configuration parameter, C_BASEADDR. Each register is 32 bits although some bits may be unused and is
accessed on a 4-byte boundary offset from the base address.
Because PLB addresses are byte addresses, XPS INTC register offsets are located at integral multiples of four from
the base address. Table 4 illustrates the registers and their offsets from the base address. The XPS INTC registers are
read as big-endian data.
Registers
The eight registers visible to the programmer are shown in Table 4 and described in this section.
These points should be considered when reading and writing to registers:
• Write of a read-only register has no affect
• Read of a write-only register returns zero
• All registers are defined for 32-bit access only; any partial-word accesses (byte, halfword) have undefined
results and return a bus error
• Unless stated otherwise, any register bits that are not mapped to inputs return zero when read and do nothing
when written
DS572 April 19, 2010
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Product Specification