DS572 Datasheet, PDF (2/26 Pages) Xilinx, Inc – LogiCORE IP XPS Interrupt

LogiCORE IP XPS Interrupt Controller (v2.01a)
Functional Description
Interrupt Controller Overview
Most CPUs provide one or more interrupt request input pins that allow external devices to request service. XPS
INTC can be used to expand the number of interrupt inputs available to the CPU and, optionally, to provide a
priority encoding scheme. The output of XPS INTC is intended to be connected to a CPU interrupt input and each
of the interrupt inputs to XPS INTC is intended to be connected to a device that can generate interrupt conditions.
Capturing, Acknowledging and Enabling Interrupt Conditions
Interrupt conditions are captured by XPS INTC and retained until explicitly cleared (also referred to as
acknowledged). Facilities are also provided to enable or disable interrupts, globally and individually. If all
interrupts are globally enabled and if at least one captured interrupt is individually enabled, an interrupt condition
is signaled upstream to the CPU.
Edge and Level-Sensitive Capture Modes
Two modes are defined for the capture of interrupt inputs as interrupt conditions.
The first, edge-sensitive capture, captures a new interrupt condition any time an active edge occurs on the interrupt
input and an interrupt condition does not already exist. (The polarity of the active edge, rising or falling, is a
per-input option.) Figure 1 illustrates the three main types of edge generation schemes, using rising edges for the
active edge in this example. In all three schemes, the device generating the interrupt provides an active edge and
some time later it produces an inactive edge in preparation for generating a new interrupt request.
X-Ref Target - Figure 1
Scheme 1
Scheme 2
Scheme 3
Interrupt
Occurs
Interrupt
Acknowledge
DS572_01_041910
Figure 1: Schemes for Generating Edges
The second mode, level-sensitive capture, causes an interrupt condition to be captured any time the input is at the
active level and an interrupt condition does not already exist. (The polarity of the active level, high or low, is an
per-input option.)
An observable difference between edge-sensitive and level-sensitive capture is:
• Active level (without subsequent transitions) can produce multiple interrupt conditions
• Edge-sensitive capture the interrupt input must cycle via an inactive edge and subsequent new active edge to
generate an additional interrupt condition
DS572 April 19, 2010
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Product Specification