DS572 Datasheet, PDF (15/26 Pages) Xilinx, Inc – LogiCORE IP XPS Interrupt

LogiCORE IP XPS Interrupt Controller (v2.01a)
All other bits will read as zeros. The Master Enable Register (MER) is shown in Figure 10 and is described in
Table 12.
X-Ref Target - Figure 10
HIE ME
w-2
w-1
Note: w - width of Data Bus
Reserved
Figure 10: Master Enable Register (MER)
DS572_10_041910
Table 12: Master Enable Register
Bits
Name
Core Access
0 : (w⁽¹⁾ – 3)
Reserved
N/A
(w⁽¹⁾ – 2)
HIE
Read / Write
(w⁽¹⁾ – 1)
ME
1. w - Width of Data Bus
Read / Write
Reset Value
All Zeros
’0’
’0’
Description
Reserved
Hardware Interrupt Enable
’0’ = Read – SW interrupts enabled
Write – No effect
’1’ = Read – HW interrupts enabled
Write – Enable HW interrupts
Master IRQ Enable
’0’ = IRQ disabled – All interrupts disabled
’1’ = IRQ enabled – All interrupts enabled
Programming XPS INTC
This section provides an overview of software initialization and communication with an XPS INTC.
The number of interrupt inputs that a XPS INTC has is set by the C_NUM_INTR_INPUTS generic described in
Table 2. The first input is always Int0 and is mapped to the LSB of the registers (except IVR and MER).
A valid interrupt input signal is any signal that provides the correct polarity and type of interrupt input. Examples
of valid interrupt inputs are rising edges, falling edges, high levels, and low levels (hardware interrupts), or
software interrupts if HIE has not been set. The polarity and type of each hardware interrupt input is specified in
the XPS INTC generics C_KIND_OF_INTR, C_KIND_OF_EDGE, and C_KIND_OF_LVL (see Table 2).
Software interrupts do not have any polarity or type associated with them, so, until HIE has been set, they are
always valid. Any valid interrupt input signal that is applied to an enabled interrupt input will generate a
corresponding interrupt request within the XPS INTC.
All interrupt requests are combined (an OR function) to form a single interrupt request output. Interrupts are
enabled individually by dedicated interrupt enable bits and collectively by a master interrupt enable bit.
During power-up or reset, the XPS INTC is put into a state where all interrupt inputs and the interrupt request
output are disabled. In order for the XPS INTC to accept interrupts and request service, the following steps are
required:
1. Each bit in the IER corresponding to an interrupt input must be set to a one. This allows the XPS INTC to begin
accepting interrupt input signals. Int0 has the highest priority, and it corresponds to the least significant bit
(LSB) in the IER.
DS572 April 19, 2010
www.xilinx.com
15
Product Specification