DS572 Datasheet, PDF (5/26 Pages) Xilinx, Inc – LogiCORE IP XPS Interrupt

LogiCORE IP XPS Interrupt Controller (v2.01a)
Table 1: XPS INTC I/O Signal Description
Port
Signal Name
Interface I/O
Initial
State
System Signals
P1 SPLB_Clk
PLB
I
-
P2 SPLB_Rst
PLB
I
-
PLB Interface Signals
P3 PLB_ABus[0 : 31]
PLB
I
-
P4 PLB_PAValid
PLB
I
-
P5
PLB_masterID
[0 : C_SPLB_MID_WIDTH - 1]
PLB
I
-
P6 PLB_RNW
PLB
I
-
P7
PLB_BE
[0 : (C_SPLB_DWIDTH/8) - 1]
PLB
I
-
P8 PLB_size[0 : 3]
PLB
I
-
P9 PLB_type[0 : 2]
PLB
I
-
P10
PLB_wrDBus
[0 : C_SPLB_DWIDTH - 1]
PLB
I
-
Unused PLB Interface Signals
P11 PLB_UABus[0 : 31]
PLB
I
-
P12 PLB_SAValid
PLB
I
-
P13 PLB_rdPrim
PLB
I
-
P14 PLB_wrPrim
P15 PLB_abort
P16 PLB_busLock
P17 PLB_MSize[0 : 1]
P18 PLB_lockErr
P19 PLB_wrBurst
P20 PLB_rdBurst
P21 PLB_wrPendReq
P22 PLB_rdPendReq
P23 PLB_wrPendPri[0 : 1]
P24 PLB_rdPendPri[0 : 1]
P25 PLB_reqPri[0 : 1]
P26 PLB_TAttribute[0 : 15]
P27 Sl_addrAck
P28 Sl_SSize[0 : 1]
PLB
I
-
PLB
I
-
PLB
I
-
PLB
I
-
PLB
I
-
PLB
I
-
PLB
I
-
PLB
I
-
PLB
I
-
PLB
I
-
PLB
I
-
PLB
I
-
PLB
I
-
PLB Slave Interface Signals
PLB
O
0
PLB
O
0
Description
PLB clock
PLB reset, active high
PLB address bus
PLB primary address valid
PLB current master identifier
PLB read not write
PLB byte enables
PLB size of requested transfer
PLB transfer type
PLB write data bus
PLB upper address bits
PLB secondary address valid
PLB secondary to primary read request
indicator
PLB secondary to primary write request
indicator
PLB abort bus request
PLB bus lock
PLB data bus width indicator
PLB lock error
PLB burst write transfer
PLB burst read transfer
PLB pending bus write request
PLB pending bus read request
PLB pending write request priority
PLB pending read request priority
PLB current request priority
PLB transfer attribute
Slave address acknowledge
Slave data bus size
DS572 April 19, 2010
www.xilinx.com
5
Product Specification