DS572 Datasheet, PDF (10/26 Pages) Xilinx, Inc – LogiCORE IP XPS Interrupt

LogiCORE IP XPS Interrupt Controller (v2.01a)
• All registers use C_NUM_INTR_INPUTS except MER which is always 2-bit wide and IVR which is always
32-bit wide
Table 4: XPS INTC Registers and Base Address Offsets
Register Name
Base Address + Offset
(Hex)
Access Type
Abbreviation Reset Value
Interrupt Status Register
C_BASEADDR + 0x0
Read / Write
ISR
All Zeros
Interrupt Pending Register
C_BASEADDR + 0x4
Read
IPR
All Zeros
Interrupt Enable Register
C_BASEADDR + 0x8
Read / Write
IER
All Zeros
Interrupt Acknowledge Register
C_BASEADDR + 0xC
Write
IAR
All Zeros
Set Interrupt Enable Bits
C_BASEADDR + 0x10
Write
SIE
All Zeros
Clear Interrupt Enable Bits
C_BASEADDR + 0x14
Write
CIE
All Zeros
Interrupt Vector Register
C_BASEADDR + 0x18
Read
IVR
All Ones
Master Enable Register
C_BASEADDR + 0x1C Read / Write
MER
All Zeros
1. If the number of interrupt inputs is less than the data bus width, the inputs will start with INT0. INT0 maps to the LSB of the ISR,
IPR, IER, IAR, SIE, CIE, and additional inputs correspond sequentially to successive bits to the left
Interrupt Status Register (ISR)
When read, the contents of this register indicate the presence or absence of an active interrupt signal. Each bit in this
register that is set to a 1 indicates an active interrupt signal on the corresponding interrupt input. Bits that are 0 are
not active. The bits in the ISR are independent of the interrupt enable bits in the IER. See the Interrupt Enable
Register (IER), page 11 for interrupt status bits that is masked by disabled interrupts.
The ISR register is writable by software until the Hardware Interrupt Enable (HIE) bit in the MER has been set. Once
that bit has been set, software can no longer write to the ISR. Given these restrictions, when this register is written
to, any data bits that are set to 1 will activate the corresponding interrupt, just as if a hardware input became active.
Data bits that are zero have no effect.
This allows software to generate interrupts for test purposes until the HIE bit has been set. Once HIE has been set
(enabling the hardware interrupt inputs), then writing to this register does nothing. If there are fewer interrupt
inputs than the width of the data bus, writing a 1 to a non-existing interrupt input does nothing and reading it will
return zero. The Interrupt Status Register (ISR) is shown in Figure 3 and the bits are described in Table 5.
X-Ref Target - Figure 3
INT(n) INT(n-2) INT(n-4)
INT(0)
0 1 2 3 45
w-2 w-1
INT(n-1) ^INT(n-3)
Note: w - width of Data Bus
INT(n-5) - INT(1)
Figure 3: Interrupt Status Register (ISR)
DS572_03_041910
Table 5: Interrupt Status Register
Bits
Name
Core Access
0 : (w⁽¹⁾ –1)
INT(n) – INT(0)
(n ≤ w – 1 )
Read / Write
1. w - Width of Data Bus
Reset Value
All Zeros
Description
Interrupt Input (n) – Interrupt Input (0)
’0’ = Not active
’1’ = Active
DS572 April 19, 2010
www.xilinx.com
10
Product Specification