DS572 Datasheet, PDF (16/26 Pages) Xilinx, Inc – LogiCORE IP XPS Interrupt

LogiCORE IP XPS Interrupt Controller (v2.01a)
2. The MER must be programmed based on the intended use of the XPS INTC. There are two bits in the MER: the
Hardware Interrupt Enable (HIE) and the Master IRQ Enable (ME). The ME bit must be set to enable the
interrupt request output.
3. If software testing is to be performed, the HIE bit must remain at its reset value of zero. Software testing can
now proceed by writing a one to any bit position in the ISR that corresponds to an existing interrupt input. A
corresponding interrupt request is generated if that interrupt is enabled, and interrupt handling proceeds
normally.
4. Once software testing has been completed, or if software testing is not performed, a one is written to the HIE bit,
which enables the hardware interrupt inputs and disables any further software generated interrupts.
5. After a one has been written to the HIE bit, any further writes to this bit have no effect. This feature prevents
stray pointers from accidentally generating unwanted interrupt requests, while still allowing self-test software
to perform system tests at power-up or after a reset.
Reading the ISR indicates which inputs are active. If present, the IPR indicates which enabled inputs are active.
Reading the optional IVR provides the ordinal value of the highest priority interrupt that is enabled and active.
For example, if the IVR is present, and a valid interrupt signal has occurred on the Int3 interrupt input and nothing
is active on Int2, Int1, and Int0, reading the IVR will provide a value of three. If Int0 becomes active then reading the
IVR provides a value of zero.
If no interrupts are active or it is not present, reading the IVR returns all ones.
Acknowledging an interrupt is achieved by writing a one to the corresponding bit location in the IAR. Note that
disabling an interrupt by masking it (writing a zero to the IER) does not clear the interrupt. That interrupt will
remain active but blocked until it is unmasked or cleared.
An interrupt acknowledge bit clears the corresponding interrupt request. However, if a valid interrupt signal
remains on that input (another edge occurs or an active level still exists on the corresponding interrupt input), a
new interrupt request output is generated.
Also, all interrupt requests are combined to form the Irq output so any remaining interrupt requests that have not
been acknowledged will cause a new interrupt request output to be generated.
The software can disable the interrupt request output at any time by writing a zero to the ME bit in the MER. This
effectively masks all interrupts for that XPS INTC. Alternatively, interrupt inputs can be selectively masked by
writing a zero to each bit location in the IER that corresponds to an input that is to be masked.
If present, SIE and CIE provide a convenient way to enable or disable (mask) an interrupt input without having to
read, mask off, and then write back the IER. Writing a one to any bit location(s) in the SIE sets the corresponding
bit(s) in the IER without affecting any other IER bits.
Writing a one to any bit location(s) in the CIE clears the corresponding bit(s) in the IER without affecting any other
IER bits.
Design Implementation
The target technology is an FPGA listed in the Supported Device Family field of the LogiCORE Facts table.
Device Utilization and Performance Benchmarks
Core Performance
Since the XPS INTC core will be used with other design modules in the FPGA, the utilization and timing numbers
reported in this section are estimates only, and will vary from the results reported here.
DS572 April 19, 2010
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Product Specification