DS572 Datasheet, PDF (6/26 Pages) Xilinx, Inc – LogiCORE IP XPS Interrupt

LogiCORE IP XPS Interrupt Controller (v2.01a)
Table 1: XPS INTC I/O Signal Description (Cont’d)
Port
Signal Name
Interface I/O
Initial
State
Description
P29 Sl_wait
PLB
O
0
Slave wait
P30 Sl_rearbitrate
PLB
O
0
Slave bus rearbitrate
P31 Sl_wrDAck
PLB
O
0
Slave write data acknowledge
P32 Sl_wrComp
PLB
O
0
Slave write transfer complete
P33 Sl_rdDBus[0 : C_SPLB_DWIDTH - 1]
PLB
O
0
Slave read data bus
P34 Sl_rdDAck
PLB
O
0
Slave read data acknowledge
P35 Sl_rdComp
PLB
O
0
Slave read transfer complete
P36
Sl_MBusy[0 : C_SPLB_
NUM_MASTERS - 1]
PLB
O
0
Slave busy
P37
Sl_MWrErr[0 : C_SPLB_
NUM_MASTERS - 1]
PLB
O
0
Slave write error
P38
Sl_MRdErr
[0 : C_SPLB_NUM_MASTERS - 1]
PLB
O
0
Slave read error
Unused PLB Slave Interface Signals
P39 Sl_wrBTerm
PLB
O
0
Slave terminate write burst transfer
P40 Sl_rdWdAddr[0 : 3]
PLB
O
0
Slave read word address
P41 Sl_rdBTerm
PLB
O
0
Slave terminate read burst transfer
P42
Sl_MIRQ
[0 : C_SPLB_NUM_MASTERS - 1]
PLB
O
0
Master interrupt request
INTC Interface Signals
P43 Intr[(C_NUM_INTR_INPUTS-1) : 0] ⁽¹⁾
INTC
I
-
Interrupt inputs
P44 Irq
INTC
0
0
Interrupt request output
1. Intr(0) is always the highest priority interrupt and each successive bit to the left has a corresponding lower interrupt priority
XPS INTC Design Parameters
To allow the user to create a XPS INTC that is uniquely tailored for the user’s system, certain features are
parameterizable in the XPS INTC design. This allows the user to have a design that utilizes only the resources
required by the system and runs at the best possible performance. The features that are parameterizable in the XPS
INTC core are as shown in Table 2.
DS572 April 19, 2010
www.xilinx.com
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Product Specification