DS572 Datasheet, PDF (4/26 Pages) Xilinx, Inc – LogiCORE IP XPS Interrupt

LogiCORE IP XPS Interrupt Controller (v2.01a)
The register addresses are fixed on four byte boundaries. All the registers and the data transfers to and from them
are always as wide as the data bus.
The number of interrupt inputs is configurable up to the width of the data bus, which is set by a configuration
parameter. The base address for the registers is also set by a configuration parameter.
Intc Interface
This is the logical block to connect the Intc Core to the PLB Interface in XPS INTC
Interrupt Controller Core (Intc Core)
Interrupt Controller Core consists of logical blocks as follows
• Interrupt Detection (Int Det) - For the detection of active input interrupt
• Registers (Regs) - Contains all status and control registers
• Interrupt request Generation (Irq Gen) - Generates the final output interrupt
Interrupt Detection (Int Det)
Interrupt detection can be configured for either level or edge detection for each interrupt input. If edge detection is
chosen, synchronization registers are included. Interrupt request generation is also configurable as either a pulse
output for an edge sensitive request or as a level output that is cleared when the interrupt is acknowledged.
Registers (Regs)
The interrupt controller contains programmer accessible registers that allow interrupts to be enabled, queried and
cleared under software control. For detail refer to:
• Interrupt Status Register (ISR), page 10
• Interrupt Pending Register (IPR), page 11
• Interrupt Enable Register (IER), page 11
• Interrupt Acknowledge Register (IAR), page 12
• Set Interrupt Enables (SIE), page 13
• Clear Interrupt Enables (CIE), page 13
• Interrupt Vector Register (IVR), page 14
• Master Enable Register (MER), page 14
Interrupt request Generation (Irq Gen)
This generates the final output interrupt from the interrupt controller core. The output interrupt sensitivity is
determined by the parameter. This checks for IER and MER to enable the interrupt generation. This also resets the
interrupt after acknowledge. It also writes the vector address of the active interrupt in IVR and enables the IPR for
pending interrupts.
XPS INTC I/O Signals
The XPS INTC signals are listed and described in Table 1.
DS572 April 19, 2010
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