DS572 Datasheet, PDF (13/26 Pages) Xilinx, Inc – LogiCORE IP XPS Interrupt

LogiCORE IP XPS Interrupt Controller (v2.01a)
Set Interrupt Enables (SIE)
SIE is a location used to set IER bits in a single atomic operation, rather than using a read/modify/write sequence.
Writing a one to a bit location in SIE will set the corresponding bit in the IER.
Writing zeros does nothing, as does writing a one to a bit location that corresponds to a non-existing interrupt input.
The SIE is optional in the XPS INTC and can be parameterized out by setting C_HAS_SIE = 0.
The Set Interrupt Enables (SIE) register is shown in Figure 7 and the bits are described in Table 9.
X-Ref Target - Figure 7
INT(n) INT(n-2) INT(n-4)
INT(0)
0 1 2 3 45
w-2 w-1
INT(n-1) INT(n-3)
Note: w - width of Data Bus
INT(n-5) - INT(1)
Figure 7: Set Interrupt Enables (SIE) Register
DS572_07_041910
Table 9: Set Interrupt Enables
Bits
Name
0 : (w⁽¹⁾ – 1)
INT(n) – INT(0)
(n ≤ w – 1 )
1. w - Width of Data Bus
Core
Access
Write
Reset Value
All Zeros
Description
Interrupt Input (n) – Interrupt Input (0)
’1’ = Set IER bit
’0’ = No action
Clear Interrupt Enables (CIE)
CIE is a location used to clear IER bits in a single atomic operation, rather than using a read/modify/write
sequence.
Writing a one to a bit location in CIE will clear the corresponding bit in the IER.
Writing zeros does nothing, as does writing a one to a bit location that corresponds to a non-existing interrupt input.
The CIE is also optional in the XPS INTC and can be parameterized out by setting C_HAS_CIE = 0.
The Clear Interrupt Enables (CIE) register is shown in Figure 8 and the bits are described in Table 10.
X-Ref Target - Figure 8
INT(n) INT(n-2) INT(n-4)
INT(0)
0 1 2 3 45
w-2 w-1
INT(n-1) INT(n-3)
Note: w - width of Data Bus
INT(n-5) - INT(1)
Figure 8: Clear Interrupt Enables (CIE) Register
DS572_08_041910
DS572 April 19, 2010
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