DS572 Datasheet, PDF (11/26 Pages) Xilinx, Inc – LogiCORE IP XPS Interrupt

LogiCORE IP XPS Interrupt Controller (v2.01a)
Interrupt Pending Register (IPR)
This is an optional read only register in the XPS INTC and can be parameterized out by setting C_HAS_IPR = 0.
Reading the contents of this register indicates the presence or absence of an active interrupt signal that is also
enabled.
Each bit in this register is the logical AND of the bits in the ISR and the IER. If there are fewer interrupt inputs than
the width of the data bus, reading a non-existing interrupt input will return zero. The Interrupt Pending Register
(IPR) is shown in Figure 4 and the bits are described in Table 6.
X-Ref Target - Figure 4
INT(n) INT(n-2) INT(n-4)
INT(0)
0 1 2 3 45
w-2 w-1
INT(n-1) ^INT(n-3)
Note: w - width of Data Bus
INT(n-5) - INT(1)
Figure 4: Interrupt Pending Register (IPR)
DS572_05_041910
Table 6: Interrupt Pending Register
Bits
Name
Core Access
0 : (w)⁽¹⁾ – 1)
INT(n) – INT(0)
(n ≤ w – 1 )
Read
1. w - Width of Data Bus
Reset Value
All Zeros
Description
Interrupt Input (n) – Interrupt Input (0)
’0’ = Not active
’1’ = Active
Interrupt Enable Register (IER)
This is a read/write register. Writing a 1 to a bit in this register enables the corresponding ISR bit to cause assertion
of the INTC output. An IER bit set to '0' does not inhibit an interrupt condition from being captured, just reported.
Writing a 0 to a bit disables, or masks, will disable the generation of interrupt output for corresponding interrupt
input signal. Note however, that disabling an interrupt input is not the same as clearing it. Disabling an active
interrupt blocks that interrupt from reaching the IRQ output, but as soon as it is re-enabled the interrupt will
immediately generate a request on the IRQ output. An interrupt must be cleared by writing to the Interrupt
Acknowledge Register as described below. Reading the IER indicates which interrupt inputs are enabled, where a
one indicates the input is enabled and a zero indicates the input is disabled.
If there are fewer interrupt inputs than the width of the data bus, writing a 1 to a non-existing interrupt input does
nothing and reading it will return zero. The Interrupt Enable Register (IER) is shown in Figure 5 and the bits are
described in Table 7.
DS572 April 19, 2010
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