DS572 Datasheet, PDF (24/26 Pages) Xilinx, Inc – LogiCORE IP XPS Interrupt

LogiCORE IP XPS Interrupt Controller (v2.01a)
X-Ref Target - Figure 14
X-Ref Target - Figure 15
MicroBlaze
Processor
MPMC
XPS CDMA XPS CDMA
Device Under
Test (DUT)
PLBV46
XPS BRAM
XPS INTC
XPS GPIO
XPS UART
Lite
MDM
DS572_14_041910
Figure 14: Spartan-6 FPGA System with the XPS Interrupt Controller as the DUT
XCL
XCL
MPMC
XPS CDMA XPS CDMA ^{Device Under}
Test (DUT)
MicroBlaze
Processor
PLBV46
XPS BRAM XPS INTC
XPS GPIO
XPS UART
Lite
MDM
DS572_15_041910
Figure 15: Virtex-6 FPGA System with the XPS Interrupt Controller as the DUT
The target FPGA was then filled with logic to drive the LUT and BRAM utilization to approximately 70% and the
I/O utilization to approximately 80%. Using the default tool options and the slowest speed grade for the target
FPGA, the resulting target F_MAX numbers are shown in Table 19.
Table 19: XPS Interrupt Controller System Performance
Target FPGA
S3A700 -4
Target F_MAX (MHz)
90
V4FX60 -10
100
V5LXT50 -1
120
V6LXT130-1
150
S6LXT45-2
100
The target F_MAX is influenced by the exact system and is provided for guidance. It is not a guaranteed value across
all systems.
Specification Exceptions
N/A
DS572 April 19, 2010
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Product Specification