DS572 Datasheet, PDF (8/26 Pages) Xilinx, Inc – LogiCORE IP XPS Interrupt

LogiCORE IP XPS Interrupt Controller (v2.01a)
Table 2: XPS INTC Design Parameters (Cont’d)
Generic
Feature /
Description
Parameter Name
Allowable Values
Default
Value
VHDL
Type
G17 Indicates the presence of CIE
C_HAS_CIE
0 = Not Present
1 = Present
1
integer
G18 Indicates the presence of IVR
C_HAS_IVR
0 = Not Present
1 = Present
1
integer
G19 Indicates level or edge active Irq C_IRQ_IS_LEVEL
0 = Active Edge
1 = Active Level
1
integer
G20
Indicates the sense of the Irq
output
C_IRQ_ACTIVE
0 = Falling / Low
1 = Rising / High
1
std_logic
1. C_BASEADDR and C_HIGHADDR give the first and last addresses, respectively, of the address range assigned to the XPS INTC.
The size in bytes, C_HIGHADDR - C_BASEADDR + 1, and the alignment of the address range must be a power of two (to allow
simple decoding) and greater than or equal to 32 (to accommodate the eight 32-bit XPS INTC registers)
2. C_BASEADDR must be aligned to the address range size. In other words, it must be a multiple of the address range size
3. No default value is specified to ensure that the actual value is set i.e. if the value is not set, a compiler error will be generated
4. If the size and alignment rules are met then C_HIGHADDR = C_BASEADDR+2**p-1 for some p >= 5; the low-order p bits of
C_BASEADDR are '0'; the low-order p bits of C_HIGHADDR are '1'; and the remaining corresponding bit positions are equal. As
the value of p increases the resources and time needed to decode the address range decrease and the amount of the overall
system address map consumed by XPS INTC increases. For example:
C_BASEADDR = 0x70800000
C_HIGHADDR = 0x7080001F
provides the maximum address decode resolution, requiring the upper 27 address bits to be decoded.
Conversely,
C_BASEADDR = 0x70000000
C_HIGHADDR = 0x7FFFFFFF
will reduce the address decoding logic for an XPS INTC (only the 4 upper address bits), resulting in a smaller and faster address
decode, which consumes one sixteenth of the system address map
5. Point-to-point bus topology is not allowed in this version of XPS INTC
6. Burst is not supported for this version of XPS INTC
7. A little-endian vector of width same as the data bus containing a 0 or 1 in each position corresponding to an interrupt input
XPS INTC Parameter - Port Dependencies
The dependencies between the XPS INTC core design parameters and I/O signals are described in Table 3. In
addition, when certain features are parameterized out of the design, the related logic will no longer be a part of the
design. The unused input signals and related output signals are set to a specified value.
Table 3: XPS INTC Parameter-Port Dependencies
Generic
or port
Name
Affects
Depends
Relationship Description
G5 C_SPLB_DWIDTH
G7 C_SPLB_NUM_MASTERS
G8 C_SPLB_MID_WIDTH
G9 C_SPLB_NATIVE_DWIDTH
Design Parameters
P7, P10,
P33
-
P36, P37,
P38, P42,
-
G8
P5
G7
G11
-
Affects number of bits in data bus
Affects the width of busy and error signals
Affects the width of current master identifier
signals and depends on
log₂(C_SPLB_NUM_MASTERS) with a
minimum value of 1
C_NUM_INTR_INPUTS <=
C_SPLB_NATIVE_DWIDTH
DS572 April 19, 2010
www.xilinx.com
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Product Specification