DS572 Datasheet, PDF (22/26 Pages) Xilinx, Inc – LogiCORE IP XPS Interrupt

LogiCORE IP XPS Interrupt Controller (v2.01a)
The XPS INTC resource utilization for various parameter combinations measured with the Spartan-6 FPGA as the
target device is detailed in Table 18.
Table 18: FPGA Performance and Resource Utilization Benchmarks the Spartan-6 FPGA
(xc6slx45t-2-fgg484)
Parameter Values
Device Resources
Performance
F_{MAX (MHZ)}
1
0
0
0
0
40
63
66
145
1
1
0
0
0
41
64
67
156
1
0
1
0
0
40
63
66
143
1
0
0
1
0
36
64
68
142
1
0
0
0
1
39
64
68
145
1
1
1
1
1
39
67
71
145
2
1
1
1
1
43
79
82
155
2
0
0
0
0
39
64
68
145
4
1
1
1
1
39
67
71
165
4
0
0
0
0
43
79
82
164
8
1
1
1
1
70
147
149
143
8
0
0
0
0
66
119
113
147
16
1
1
1
1
47
87
86
143
16
0
0
0
0
70
147
149
162
32
1
1
1
1
40
63
66
111
32
0
0
0
0
196
233
255
126
1. Above numbers are reported by tool for clock of period constraint of 10ns
System Performance
To measure the system performance (F_MAX) of this core, the xps_intc_v2_01_a core was added to a Virtex-4 FPGA
system, a Virtex-5 FPGA system, a Spartan-3A FPGA system, a Spartan-6 system, and a Virtex-6 system as the
Device Under Test (DUT) as shown in Figure 11, Figure 12, Figure 13, Figure 14, and Figure 15.
Because the XPS Interrupt Controller core will be used with other design modules in the FPGA, the utilization and
timing numbers reported in this section are estimates only. When this core is combined with other designs in the
system, the utilization of FPGA resources and timing of the core design will vary from the results reported here.
DS572 April 19, 2010
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Product Specification