DS572 Datasheet, PDF (3/26 Pages) Xilinx, Inc – LogiCORE IP XPS Interrupt

LogiCORE IP XPS Interrupt Controller (v2.01a)
Timing Requirement
There is a timing requirement on interrupt input signaling. After an edge for an edge-sensitive interrupt input
signal or after the establishment of the active level for a level-sensitive interrupt input signal, the signal must
remain stable for a minimum interval to guarantee capture. If the device driving the interrupt input is on the same
clock domain as XPS INTC, then this interval is one clock period with standard synchronous setup and hold
requirements. If the driving device is on an unrelated clock, the interval must be at least an XPS INTC clock period
plus a suitable margin. The margin is chosen by specification to be 20% of the XPS INTC clock period.
Interrupt Vector Register
If an optional Interrupt Vector Register is opted in the XPS INTC, then a priority relationship is established between
the interrupt inputs (lower number, higher priority). The register returns the number attached to the individually
enabled interrupt with highest priority. This can be used to expedite the speed at which software can select the
appropriate interrupt service routine (software vectoring).
XPS INTC Organization
The XPS INTC is organized mainly into the following functional units as shown in Figure 2:
• PLB interface - Provides the interface to Processor Local Bus
• Interrupt Detect (Int Det) - Detects the valid interrupt from all the interrupt inputs
• Programmer Registers (Regs) - Registers used to program and control the operation of interrupt controller
• Request Generation (Irq Gen) - Generate the output interrupt reques
X-Ref Target - Figure 2
XPS INTC
INTC Core
Intr
Irq
Int Det
Irq Gen
PLB
Interface
IP2Bus_Error
IP2Bus_WrAck
IP2Bus_RdAck
Bus2IP_CS
Bus2IP_RNW
Bus2IP_RdCE
Bus2IP_WrCE
Bus2IP_Data
Bus2IP_Addr
IP2Bus_Data
INTC
Interface
Valid_rd
Valid_wr
Wr_data
Reg_Addr
Rd_data
Registers
ISR
IPR
IER
IAR
SIE
CIE
IVR
MER
Note:
Intc Interface: Design module does not exist by this name. This interface is part of top-level XPS INTC.
Figure 2: XPS INTC Block Diagram
DS572_02_101405
PLB Interface
PLB interface provides a slave interface on the PLB for transferring data between the INTC and the processor. The
XPS INTC registers are memory mapped into the PLB address space and data transfers occur using PLB byte
enables.
DS572 April 19, 2010
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