DS572 Datasheet, PDF (14/26 Pages) Xilinx, Inc – LogiCORE IP XPS Interrupt

LogiCORE IP XPS Interrupt Controller (v2.01a)
Table 10: Clear Interrupt Enables
Bits
Name
Core Access
0 : (w⁽¹⁾ – 1)
INT(n) – INT(0)
(n ≤ w – 1 )
Write
1. w - Width of Data Bus
Reset Value
All Zeros
Description
Interrupt Input (n) – Interrupt Input (0)
’1’ = Clear IER bit
’0’ = No action
Interrupt Vector Register (IVR)
The IVR is a read-only register and contains the ordinal value of the highest priority, enabled, active interrupt input.
INT0 (always the LSB) is the highest priority interrupt input and each successive input to the left has a
correspondingly lower interrupt priority.
If no interrupt inputs are active then the IVR will contain all ones. The IVR is optional in the XPS INTC and can be
parameterized out by setting C_HAS_IVR = 0. The Interrupt Vector Register (IVR) is shown in Figure 9 and
described in Table 11.
X-Ref Target - Figure 9
0
w-1
Note: w - width of Data Bus
Interrupt Vector Number
Figure 9: Interrupt Vector Register (IVR)
DS572_09_041910
Table 11: Interrupt Vector Register
Bits
Name
Core Access
0 : (w⁽¹⁾ – 1)
Interrupt Vector
Number
Read
1. w - Width of Data Bus
Reset Value
All Ones
Description
Ordinal of highest priority, enabled, active
interrupt input
Master Enable Register (MER)
This is a two bit, read/write register. The two bits are mapped to the two least significant bits of the location.
The least significant bit contains the Master Enable (ME) bit and the next bit contains the Hardware Interrupt
Enable (HIE) bit.
Writing a 1 to the ME bit enables the IRQ output signal. Writing a 0 to the ME bit disables the IRQ output, effectively
masking all interrupt inputs.
The HIE bit is a write once bit. At reset this bit is reset to zero, allowing software to write to the ISR to generate
interrupts for testing purposes, and disabling any hardware interrupt inputs.
Writing a one to this bit enables the hardware interrupt inputs and disables software generated inputs. Writing a
one also disables any further changes to this bit until the device has been reset.
Writing ones or zeros to any other bit location does nothing. When read, this register will reflect the state of the ME
and HIE bits.
DS572 April 19, 2010
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Product Specification