DS572 Datasheet, PDF (12/26 Pages) Xilinx, Inc – LogiCORE IP XPS Interrupt

LogiCORE IP XPS Interrupt Controller (v2.01a)
X-Ref Target - Figure 5
INT(n) INT(n-2) INT(n-4)
INT(0)
0 1 2 3 45
w-2 w-1
INT(n-1) INT(n-3)
Note: w - width of Data Bus
INT(n-5) - INT(1)
Figure 5: Interrupt Enable Register (IER)
DS572_05_041910
Table 7: Interrupt Enable Register
Bits
Name
Core
Access
0 : (w⁽¹⁾ – 1)
INT(n) – INT(0)
(n ≤ w – 1 )
Read / Write
1. w - Width of Data Bus
Reset Value
All Zeros
Description
Interrupt Input (n) – Interrupt Input (0)
’1’ = Interrupt enabled
’0’ = Interrupt disabled
Interrupt Acknowledge Register (IAR)
The IAR is a write only location that clears the interrupt request associated with selected interrupt inputs. Note that
writing one to a bit in IAR clears the corresponding bit in ISR and also clears the same bit itself in IAR.
Writing a one to a bit location in the IAR will clear the interrupt request that was generated by the corresponding
interrupt input. An interrupt input that is active and masked by writing a 0 to the corresponding bit in the IER will
remain active until cleared by acknowledging it. Unmasking an active interrupt will cause an interrupt request
output to be generated (if the ME bit in the MER is set).
Writing zeros does nothing as does writing a one to a bit that does not correspond to an active input or for which an
interrupt input does not exist. The Interrupt Acknowledge Register (IAR) is shown in Figure 6 and the bits are
described in Table 8.
X-Ref Target - Figure 6
INT(n) INT(n-2) INT(n-4)
INT(0)
0 1 2 3 45
w-2 w-1
INT(n-1) INT(n-3)
Note: w - width of Data Bus
INT(n-5) - INT(1)
Figure 6: Interrupt Acknowledge Register (IAR)
DS572_06_041910
Table 8: Interrupt Acknowledge Register
Bits
Name
Core Access
0 : (w⁽¹⁾ – 1)
INT(n) – INT(0)
(n ≤ w – 1 )
Write
1. w - Width of Data Bus
Reset Value
All Zeros
Description
Interrupt Input (n) – Interrupt Input (0)
’1’ = Clear Interrupt
’0’ = No action
DS572 April 19, 2010
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Product Specification