DS572 Datasheet, PDF (1/26 Pages) Xilinx, Inc – LogiCORE IP XPS Interrupt

DS572 April 19, 2010
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LogiCORE IP XPS Interrupt
Controller (v2.01a)
0
Product Specification
Introduction
The LogiCORE IP XPS Interrupt Controller (XPS INTC)
concentrates multiple interrupt inputs from peripheral
devices to a single interrupt output to the system
processor. The registers for checking, enabling and
acknowledging interrupts are accessed through a slave
interface for the Processor Local Bus (PLB V4.6). The
number of interrupts and other aspects can be tailored
to the target system.
Features
• Connects as a 32-bit slave on PLB V4.6 bus of 32, 64
and 128-bit data width
• Configurable number of (up to 32) interrupt inputs
• Single interrupt output
• Easily cascaded to provide additional interrupt
inputs
• Priority between interrupt requests is determined
by vector position. The least significant bit (LSB, in
this case bit 0) has the highest priority
• Interrupt Enable Register for selectively disabling
individual interrupt inputs
• Master Enable Register for disabling interrupt
request output
• Each input is configurable for edge or level
sensitivity; edge sensitivity can be configured for
rising or falling; level sensitivity can be active-high
or low
• Automatic edge synchronization when inputs are
configured for edge sensitivity
• Output interrupt request pin is configurable for
edge or level generation - edge generation
configurable for rising or falling; level generation
configurable for active-high or low
LogiCORE™ Facts
Supported Device
Family
Core Specifics
Spartan^®-6, Virtex^®-6/6CX,
Spartan-3, Spartan-3A,
Spartan-3E, Automotive
Spartan-3/3E/3A/3A DSP,
Spartan-3 ADSP, Virtex-4,
QVirtex-4, QRVirtex-4,Virtex-5/5FX
Version of Core
xps_intc
v2.01a
Resources Used
Min
Max
Slices
FFs
LUTs
See Table 13, Table 14, Table 15,
Table 16, Table 17, and Table 18
Block RAMs
N/A
Provided with Core
Documentation
Product Specification
Design File Formats VHDL
Constraints File
N/A
Verification
N/A
Instantiation Template N/A
Reference Designs &
Application Notes
N/A
Design Tool Requirements
Xilinx Implementation
Tools
ISE 12.1
Verification
MentorGraphics ModelSim 6.5c
and above
Simulation
MentorGraphics ModelSim 6.5c
and above
Synthesis
XST
Support
Provided by Xilinx, Inc.
© Copyright 2007-2010 Xilinx, Inc. XILINX, the Xilinx logo, Virtex, Spartan, ISE and other designated brands included herein are trademarks of Xilinx in the United
States and other countries. All other trademarks are the property of their respective owners.
DS572 April 19, 2010
www.xilinx.com
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Product Specification