DS506 Datasheet, PDF (9/19 Pages) Xilinx, Inc – LogiCORE IP Endpoint v3.7

LogiCORE IP Endpoint v3.7 for PCI Express^®
Table 5: PCI Express Interface Signals for the 8-lane Endpoint Core
Lane
Number
Name
Direction
Description
0
pci_exp_txp0
Output PCI Express Transmit Positive: Serial Differential Output 0 (+)
0
pci_exp_txn0
Output PCI Express Transmit Negative: Serial Differential Output 0 (–)
0
pci_exp_rxp0
Input PCI Express Receive Positive: Serial Differential Input 0 (+)
0
pci_exp_rxn0
Input PCI Express Receive Negative: Serial Differential Input 0 (–)
1
pci_exp_txp1
Output PCI Express Transmit Positive: Serial Differential Output 1 (+)
1
pci_exp_txn1
Output PCI Express Transmit Negative: Serial Differential Output 1 (–)
1
pci_exp_rxp1
Input PCI Express Receive Positive: Serial Differential Input 1 (+)
1
pci_exp_rxn1
Input PCI Express Receive Negative: Serial Differential Input 1 (–)
2
pci_exp_txp2
Output PCI Express Transmit Positive: Serial Differential Output 2 (+)
2
pci_exp_txn2
Output PCI Express Transmit Negative: Serial Differential Output 2 (–)
2
pci_exp_rxp2
Input PCI Express Receive Positive: Serial Differential Input 2 (+)
2
pci_exp_rxn2
Input PCI Express Receive Negative: Serial Differential Input 2 (–)
3
pci_exp_txp3
Output PCI Express Transmit Positive: Serial Differential Output 3 (+)
3
pci_exp_txn3
Output PCI Express Transmit Negative: Serial Differential Output 3 (–)
3
pci_exp_rxp3
Input PCI Express Receive Positive: Serial Differential Input 3 (+)
3
pci_exp_rxn3
Input PCI Express Receive Negative: Serial Differential Input 3 (–)
4
pci_exp_txp4
Output PCI Express Transmit Positive: Serial Differential Output 4 (+)
4
pci_exp_txn4
Output PCI Express Transmit Negative: Serial Differential Output 4 (–)
4
pci_exp_rxp4
Input PCI Express Receive Positive: Serial Differential Input 4 (+)
4
pci_exp_rxn4
Input PCI Express Receive Negative: Serial Differential Input 4 (–)
5
pci_exp_txp5
Output PCI Express Transmit Positive: Serial Differential Output 5 (+)
5
pci_exp_txn5
Output PCI Express Transmit Negative: Serial Differential Output 5 (–)
5
pci_exp_rxp5
Input PCI Express Receive Positive: Serial Differential Input 5 (+)
5
pci_exp_rxn5
Input PCI Express Receive Negative: Serial Differential Input 5 (–)
6
pci_exp_txp6
Output PCI Express Transmit Positive: Serial Differential Output 6 (+)
6
pci_exp_txn6
Output PCI Express Transmit Negative: Serial Differential Output 6 (–)
6
pci_exp_rxp6
Input PCI Express Receive Positive: Serial Differential Input 6 (+)
6
pci_exp_rxn6
Input PCI Express Receive Negative: Serial Differential Input 6 (–)
7
pci_exp_txp7
Output PCI Express Transmit Positive: Serial Differential Output 7 (+)
7
pci_exp_txn7
Output PCI Express Transmit Negative: Serial Differential Output 7 (–)
7
pci_exp_rxp7
Input PCI Express Receive Positive: Serial Differential Input 7 (+)
7
pci_exp_rxn7
Input PCI Express Receive Negative: Serial Differential Input 7 (–)
Configuration Interface
The Configuration (CFG) interface provides a mechanism for the user design to inspect the state of the
Endpoint core’s PCI Express configuration space. The user provides a 10-bit configuration address that
selects one of the 1024 configuration space double word (DWORD) registers. The endpoint then returns
DS506 April 19, 2010
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Product Specification