DS506 Datasheet, PDF (12/19 Pages) Xilinx, Inc – LogiCORE IP Endpoint v3.7

LogiCORE IP Endpoint v3.7 for PCI Express^®
Table 6: Configuration Interface Signals (Cont’d)
Name
Direction
Description
cfg_command[15:0]
Output
Configuration Command: Command register from the
Configuration Space Header.
cfg_dstatus[15:0]
Output
Configuration Device Status: Device status register from the
PCI Express Extended Capability Structure.
cfg_dcommand[15:0]
Output
Configuration Device Command: Device control register
from the PCI Express Extended Capability Structure.
cfg_lstatus[15:0]
Output
Configuration Link Status: Link status register from the PCI
Express Extended Capability Structure.
cfg_lcommand[15:0]
Output
Configuration Link Command: Link control register from the
PCI Express Extended Capability Structure.
cfg_cfg[1023:0]
Input
Configuration Configure: This 1024-bit input port is used to
configure core options. This port must by driven by a1024-bit
constant valued binary pattern by the user.
cfg_err_ur_n
Input
Configuration Error Unsupported Request: The user can
assert this signal to report that an unsupported request was
received. Active low.
cfg_err_cor_n
Input
Configuration Error Correctable Error: The user can assert
this signal to report that a correctable error was detected.
Active low.
cfg_to_turnoff_n
Output
Configuration To Turnoff: Output that notifies the user that a
PME_TURN_Off message has been received and the CMM
will start polling the cfg_turnoff_ok_n input coming in from the
user. Once cfg_turnoff_ok_n is asserted, CMM sends a
PME_To_Ack message to the upstream device. Active low.
cfg_pm_wake_n
Input
Configuration Power Management Wake: A one-clock cycle
active low assertion on this signal enables the core to generate
and send a Power Management PME Message TLP to the
upstream link partner.
Note: The user is required to assert this input only under
stable link conditions as reported on the
cfg_pcie_link_state[2:0] bus. Assertion of this signal when the
PCI Express Link is in transition will result in incorrect behavior
on the PCI Express Link.
cfg_pcie_link_state_n[2:0]¹
Output
PCI Express Link State: This one-hot encoded bus reports the
PCI Express Link State information to the user.
• 110b - PCI Express Link State is L0
• 101b - PCI Express Link State is L0s
• 011b - PCI Express Link State is L1
• 111b - PCI Express Link State is in transition
cfg_trn_pending_n
Input
User Transaction Pending: When asserted, sets the
Transaction Pending bit in the Device Status Register. User is
required to assert this input if the user application has not
received a completion to an upstream request. Active low.
cfg_dsn[63:0]
Input
Configuration Device Serial Number: Serial Number
Register fields of the PCI Express Device Serial Number
extended capability.
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DS506 April 19, 2010
Product Specification