DS506 Datasheet, PDF (18/19 Pages) Xilinx, Inc – LogiCORE IP Endpoint v3.7

LogiCORE IP Endpoint v3.7 for PCI Express^®
Common TRN Interface
Table 11 defines and describes the common TRN interface signals.
Table 11: Common Transaction Interface Signals
Name
Direction
Description
trn_clk
Output
Transaction Clock: Transaction and Configuration interface operations are
referenced-to and synchronous-with the rising edge of this clock. trn_clk is
unavailable when the core sys_reset_n is held asserted. trn_clk is guaranteed to
be stable at the nominal operating frequency once the core deasserts
trn_reset_n.
Product
Frequency (MHz)
1-lane 64-bit Endpoint
31.25 MHz
4-lane 64-bit Endpoint
125 MHz
8-lane 64-bit Endpoint
250 MHz
1-lane 32-bit Endpoint
62.5 MHz
4-lane 32-bit Endpoint
250 MHz
trn_reset_n
Output
Transaction Reset: Active low. User logic interacting with the Transaction and
Configuration interfaces must use trn_reset_n to return to their quiescent states.
trn_reset_n is deasserted synchronously with respect to trn_clk, sys_reset_n is
deasserted and is asserted asynchronously with sys_reset_n assertion. Note
that trn_reset_n is not asserted for core in-band reset events like Hot Reset or
Link Disable.
trn_lnk_up_n
Output
Transaction Link Up: Active low. Transaction link-up is asserted when the core
and the connected upstream link partner port are ready and able to exchange
data packets. Transaction link-up is deasserted when the core and link partner
are attempting to establish communication, and when communication with the
link partner is lost due to errors on the transmission channel. When the core is
driven to Hot Reset and Link Disable states by the link partner, trn_lnk_up_n is
deasserted and all TLPs stored in the endpoint core are lost.
Support
Xilinx provides technical support for this LogiCORE product when used as described in the product
documentation. Xilinx cannot guarantee timing, functionality, or support of product if implemented in
devices that are not defined in the documentation, if customized beyond that allowed in the product
documentation, or if changes are made to any section of the design labeled DO NOT MODIFY.
Ordering Information
The Endpoint for PCIe core is provided under the SignOnce IP Site License and can be generated using
the Xilinx CORE Generator system v12.1or higher. The CORE Generator system is shipped with Xilinx
ISE Foundation Series Development software.
A simulation evaluation license for the core is shipped with the CORE Generator system. To access the
full functionality of the core, including FPGA bitstream generation, a full license must be obtained from
Xilinx. For more information, please visit the product page for this core.
Please contact your local Xilinx sales representative for pricing and availability of additional Xilinx
LogiCORE modules and software. Information about additional Xilinx LogiCORE modules is available
on the Xilinx IP Center.
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DS506 April 19, 2010
Product Specification